Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.51	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	27	101	78.91

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	27	101	78.91	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2436

1

T7

24

T4

6

T8

24

auto[1]

824

1

T56

10

T57

26

T58

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	448	1			T172	18		T45	18		T56	10
values[1]	288	1			T94	4		T214	2		T59	14
values[2]	296	1			T11	24		T12	12		T120	6
values[3]	534	1			T9	26		T43	8		T180	2
values[4]	362	1			T8	24		T177	6		T175	2
values[5]	392	1			T174	10		T75	8		T57	26
values[6]	408	1			T64	8		T92	16		T93	6
values[7]	532	1			T7	24		T4	6		T29	30

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	346	1			T7	24		T90	4		T196	30
values[1]	430	1			T177	6		T174	10		T91	10
values[2]	544	1			T172	18		T44	10		T78	18
values[3]	298	1			T4	6		T11	24		T92	16
values[4]	352	1			T55	14		T45	18		T62	26
values[5]	416	1			T12	12		T64	8		T93	6
values[6]	514	1			T180	2		T65	32		T67	34
values[7]	360	1			T8	24		T9	26		T43	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	27	101	78.91	27

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[3]]	0	1	1
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[4]]	[values[3]]	0	1	1
[auto[1]]	[values[4]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[5]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2]]	0	1	1
[auto[1]]	[values[6]]	[values[4]]	0	1	1
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[4] , values[5]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	26	1			T201	26		-	-		-	-
auto[0]	values[0]	values[1]	32	1			T302	32		-	-		-	-
auto[0]	values[0]	values[2]	32	1			T172	18		T197	14		-	-
auto[0]	values[0]	values[3]	40	1			T209	10		T303	14		T263	2
auto[0]	values[0]	values[4]	36	1			T45	18		T184	12		T261	6
auto[0]	values[0]	values[5]	46	1			T210	26		T207	18		T240	2
auto[0]	values[0]	values[6]	90	1			T242	32		T208	12		T257	32
auto[0]	values[0]	values[7]	14	1			T222	2		T234	12		-	-
auto[0]	values[1]	values[0]	8	1			T167	6		T274	2		-	-
auto[0]	values[1]	values[1]	42	1			T191	24		T251	8		T269	10
auto[0]	values[1]	values[2]	62	1			T236	20		T304	16		T305	26
auto[0]	values[1]	values[3]	4	1			T94	4		-	-		-	-
auto[0]	values[1]	values[4]	6	1			T66	6		-	-		-	-
auto[0]	values[1]	values[5]	18	1			T114	18		-	-		-	-
auto[0]	values[1]	values[6]	40	1			T306	24		T219	12		T258	4
auto[0]	values[1]	values[7]	24	1			T214	2		T59	14		T80	8
auto[0]	values[2]	values[0]	2	1			T266	2		-	-		-	-
auto[0]	values[2]	values[1]	22	1			T260	4		T87	6		T213	12
auto[0]	values[2]	values[2]	20	1			T232	16		T216	4		-	-
auto[0]	values[2]	values[3]	60	1			T11	24		T120	6		T60	4
auto[0]	values[2]	values[4]	20	1			T238	16		T226	4		-	-
auto[0]	values[2]	values[5]	50	1			T12	12		T30	2		T307	18
auto[0]	values[2]	values[6]	26	1			T308	10		T220	16		-	-
auto[0]	values[2]	values[7]	28	1			T265	6		T241	8		T116	14
auto[0]	values[3]	values[0]	84	1			T90	4		T270	14		T267	2
auto[0]	values[3]	values[1]	50	1			T309	8		T310	18		T311	24
auto[0]	values[3]	values[2]	86	1			T312	18		T95	14		T313	32
auto[0]	values[3]	values[3]	18	1			T314	18		-	-		-	-
auto[0]	values[3]	values[4]	28	1			T315	28		-	-		-	-
auto[0]	values[3]	values[5]	94	1			T176	12		T173	12		T85	2
auto[0]	values[3]	values[6]	74	1			T180	2		T65	32		T243	18
auto[0]	values[3]	values[7]	34	1			T9	26		T43	8		-	-
auto[0]	values[4]	values[0]	64	1			T224	36		T235	16		T211	10
auto[0]	values[4]	values[1]	10	1			T177	6		T316	4		-	-
auto[0]	values[4]	values[2]	14	1			T218	10		T193	2		T186	2
auto[0]	values[4]	values[3]	36	1			T169	2		T86	14		T247	20
auto[0]	values[4]	values[4]	18	1			T246	18		-	-		-	-
auto[0]	values[4]	values[5]	28	1			T61	26		T317	2		-	-
auto[0]	values[4]	values[6]	46	1			T318	12		T319	34		-	-
auto[0]	values[4]	values[7]	72	1			T8	24		T175	2		T250	26
auto[0]	values[5]	values[0]	18	1			T108	12		T115	6		-	-
auto[0]	values[5]	values[1]	40	1			T174	10		T212	18		T320	10
auto[0]	values[5]	values[2]	44	1			T277	8		T195	36		-	-
auto[0]	values[5]	values[3]	32	1			T75	8		T321	2		T190	4
auto[0]	values[5]	values[4]	34	1			T182	16		T322	16		T253	2
auto[0]	values[5]	values[5]	60	1			T89	6		T231	34		T237	18
auto[0]	values[5]	values[6]	18	1			T179	18		-	-		-	-
auto[0]	values[5]	values[7]	24	1			T113	10		T205	14		-	-
auto[0]	values[6]	values[0]	10	1			T183	4		T198	6		-	-
auto[0]	values[6]	values[1]	22	1			T91	10		T268	2		T323	10
auto[0]	values[6]	values[2]	72	1			T44	10		T27	6		T271	24
auto[0]	values[6]	values[3]	28	1			T92	16		T31	12		-	-
auto[0]	values[6]	values[4]	40	1			T62	26		T280	14		-	-
auto[0]	values[6]	values[5]	48	1			T64	8		T93	6		T28	16
auto[0]	values[6]	values[6]	70	1			T203	4		T324	4		T325	34
auto[0]	values[6]	values[7]	50	1			T326	18		T262	12		T327	20
auto[0]	values[7]	values[0]	66	1			T7	24		T196	30		T256	4
auto[0]	values[7]	values[1]	12	1			T165	8		T272	4		-	-
auto[0]	values[7]	values[2]	84	1			T78	18		T264	10		T328	24
auto[0]	values[7]	values[3]	40	1			T4	6		T29	30		T185	4
auto[0]	values[7]	values[4]	40	1			T55	14		T178	6		T233	20
auto[0]	values[7]	values[5]	18	1			T73	18		-	-		-	-
auto[0]	values[7]	values[6]	42	1			T329	14		T330	28		-	-
auto[0]	values[7]	values[7]	20	1			T26	20		-	-		-	-
auto[1]	values[0]	values[1]	6	1			T331	6		-	-		-	-
auto[1]	values[0]	values[4]	34	1			T259	32		T228	2		-	-
auto[1]	values[0]	values[5]	22	1			T249	22		-	-		-	-
auto[1]	values[0]	values[6]	18	1			T202	18		-	-		-	-
auto[1]	values[0]	values[7]	52	1			T56	10		T58	22		T225	20
auto[1]	values[1]	values[1]	20	1			T69	20		-	-		-	-
auto[1]	values[1]	values[2]	38	1			T199	4		T229	34		-	-
auto[1]	values[1]	values[4]	14	1			T332	14		-	-		-	-
auto[1]	values[1]	values[6]	12	1			T68	12		-	-		-	-
auto[1]	values[2]	values[0]	12	1			T194	12		-	-		-	-
auto[1]	values[2]	values[2]	28	1			T333	28		-	-		-	-
auto[1]	values[2]	values[3]	2	1			T181	2		-	-		-	-
auto[1]	values[2]	values[4]	22	1			T71	22		-	-		-	-
auto[1]	values[2]	values[7]	4	1			T206	4		-	-		-	-
auto[1]	values[3]	values[2]	8	1			T282	8		-	-		-	-
auto[1]	values[3]	values[3]	20	1			T252	20		-	-		-	-
auto[1]	values[3]	values[4]	22	1			T334	22		-	-		-	-
auto[1]	values[3]	values[6]	16	1			T72	16		-	-		-	-
auto[1]	values[4]	values[1]	10	1			T215	10		-	-		-	-
auto[1]	values[4]	values[2]	44	1			T63	32		T239	12		-	-
auto[1]	values[4]	values[4]	14	1			T281	14		-	-		-	-
auto[1]	values[4]	values[7]	6	1			T192	6		-	-		-	-
auto[1]	values[5]	values[0]	10	1			T244	2		T221	4		T335	4
auto[1]	values[5]	values[1]	56	1			T245	30		T336	26		-	-
auto[1]	values[5]	values[4]	24	1			T337	24		-	-		-	-
auto[1]	values[5]	values[5]	26	1			T57	26		-	-		-	-
auto[1]	values[5]	values[6]	6	1			T338	6		-	-		-	-
auto[1]	values[6]	values[1]	46	1			T339	28		T340	18		-	-
auto[1]	values[6]	values[3]	12	1			T70	12		-	-		-	-
auto[1]	values[6]	values[5]	6	1			T341	6		-	-		-	-
auto[1]	values[6]	values[6]	4	1			T200	4		-	-		-	-
auto[1]	values[7]	values[0]	46	1			T81	16		T342	30		-	-
auto[1]	values[7]	values[1]	62	1			T284	28		T343	34		-	-
auto[1]	values[7]	values[2]	12	1			T227	12		-	-		-	-
auto[1]	values[7]	values[3]	6	1			T187	6		-	-		-	-
auto[1]	values[7]	values[6]	52	1			T67	34		T248	18		-	-
auto[1]	values[7]	values[7]	32	1			T344	14		T345	18		-	-