Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.04	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	8	52	86.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	8	52	86.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	142	1			T43	6		T92	10		T45	10
auto[ReadAddrCrossIntoMailbox]	20	1			T8	8		T120	2		T303	4
auto[ReadAddrCrossOutOfMailbox]	30	1			T8	2		T120	2		T78	8
auto[ReadAddrCrossAllMailbox]	28	1			T8	2		T78	4		T277	2
auto[ReadAddrOutsideMailbox]	822	1			T8	12		T9	2		T11	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

521

1

T8

12

T9

1

T11

3

auto[1]

521

1

T8

12

T9

1

T11

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	214	1			T11	6		T92	8		T94	2
read_ops[0x0b]	164	1			T12	2		T43	2		T64	2
read_ops[0x3b]	158	1			T8	4		T43	2		T92	2
read_ops[0x6b]	178	1			T8	8		T9	2		T43	2
read_ops[0xbb]	168	1			T8	12		T180	2		T73	2
read_ops[0xeb]	160	1			T177	2		T45	2		T174	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	8	52	86.67	8

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2
[read_ops[0x3b]]	[auto[ReadAddrCrossIntoMailbox] , auto[ReadAddrCrossOutOfMailbox]]	*	--	--	4
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	13	1			T92	4		T264	1		T169	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T92	4		T264	1		T169	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T120	1		T303	1		T283	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T120	1		T303	1		T283	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T120	1		T78	1		T303	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T120	1		T78	1		T303	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T78	1		T303	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T78	1		T303	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	84	1			T11	3		T94	1		T44	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	84	1			T11	3		T94	1		T44	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T43	1		T346	1		T311	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T43	1		T346	1		T311	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T108	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T108	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T108	1		T279	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T108	1		T279	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	75	1			T12	1		T64	1		T94	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	75	1			T12	1		T64	1		T94	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T43	1		T92	1		T179	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T43	1		T92	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T314	2		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T314	2		-	-		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	67	1			T8	2		T62	2		T56	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	67	1			T8	2		T62	2		T56	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T43	1		T45	4		T120	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T43	1		T45	4		T120	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T277	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T277	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T277	1		T267	1		T108	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T277	1		T267	1		T108	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T8	4		T9	1		T93	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	68	1			T8	4		T9	1		T93	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T180	1		T78	1		T205	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T180	1		T78	1		T205	4
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T8	4		T303	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T8	4		T303	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T8	1		T78	3		T311	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T8	1		T78	3		T311	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T8	1		T78	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T8	1		T78	1		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	56	1			T73	1		T57	1		T78	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	56	1			T73	1		T57	1		T78	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T45	1		T235	1		T179	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T45	1		T235	1		T179	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T311	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T311	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T273	1		T108	1		T314	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T273	1		T108	1		T314	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T314	1		T311	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T314	1		T311	1		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T177	1		T174	2		T62	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T177	1		T174	2		T62	2