Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	211566	1			T1	4710		T2	26		T3	1
all_pins[1]	211566	1			T1	4710		T2	26		T3	1
all_pins[2]	211566	1			T1	4710		T2	26		T3	1
all_pins[3]	211566	1			T1	4710		T2	26		T3	1
all_pins[4]	211566	1			T1	4710		T2	26		T3	1
all_pins[5]	211566	1			T1	4710		T2	26		T3	1
all_pins[6]	211566	1			T1	4710		T2	26		T3	1
all_pins[7]	211566	1			T1	4710		T2	26		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1691601	1			T1	37680		T2	208		T3	8
values[0x1]	927	1			T17	31		T40	25		T41	37
transitions[0x0=>0x1]	722	1			T17	28		T40	17		T41	27
transitions[0x1=>0x0]	727	1			T17	28		T40	18		T41	27

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	211451	1			T1	4710		T2	26		T3	1
all_pins[0]	values[0x1]	115	1			T17	2		T40	2		T41	9
all_pins[0]	transitions[0x0=>0x1]	86	1			T17	2		T41	9		T352	2
all_pins[0]	transitions[0x1=>0x0]	88	1			T17	7		T40	6		T352	5
all_pins[1]	values[0x0]	211449	1			T1	4710		T2	26		T3	1
all_pins[1]	values[0x1]	117	1			T17	7		T40	8		T352	6
all_pins[1]	transitions[0x0=>0x1]	85	1			T17	7		T40	8		T352	5
all_pins[1]	transitions[0x1=>0x0]	94	1			T17	4		T40	1		T41	1
all_pins[2]	values[0x0]	211440	1			T1	4710		T2	26		T3	1
all_pins[2]	values[0x1]	126	1			T17	4		T40	1		T41	1
all_pins[2]	transitions[0x0=>0x1]	110	1			T17	4		T40	1		T41	1
all_pins[2]	transitions[0x1=>0x0]	81	1			T17	4		T40	2		T41	1
all_pins[3]	values[0x0]	211469	1			T1	4710		T2	26		T3	1
all_pins[3]	values[0x1]	97	1			T17	4		T40	2		T41	1
all_pins[3]	transitions[0x0=>0x1]	76	1			T17	4		T40	1		T41	1
all_pins[3]	transitions[0x1=>0x0]	109	1			T17	5		T40	2		T41	4
all_pins[4]	values[0x0]	211436	1			T1	4710		T2	26		T3	1
all_pins[4]	values[0x1]	130	1			T17	5		T40	3		T41	4
all_pins[4]	transitions[0x0=>0x1]	101	1			T17	4		T40	2		T41	2
all_pins[4]	transitions[0x1=>0x0]	83	1			T17	4		T40	2		T41	1
all_pins[5]	values[0x0]	211454	1			T1	4710		T2	26		T3	1
all_pins[5]	values[0x1]	112	1			T17	5		T40	3		T41	3
all_pins[5]	transitions[0x0=>0x1]	92	1			T17	3		T40	2		T41	2
all_pins[5]	transitions[0x1=>0x0]	97	1			T17	2		T40	2		T41	9
all_pins[6]	values[0x0]	211449	1			T1	4710		T2	26		T3	1
all_pins[6]	values[0x1]	117	1			T17	4		T40	3		T41	10
all_pins[6]	transitions[0x0=>0x1]	90	1			T17	4		T40	2		T41	7
all_pins[6]	transitions[0x1=>0x0]	86	1			T40	2		T41	6		T352	1
all_pins[7]	values[0x0]	211453	1			T1	4710		T2	26		T3	1
all_pins[7]	values[0x1]	113	1			T40	3		T41	9		T352	1
all_pins[7]	transitions[0x0=>0x1]	82	1			T40	1		T41	5		T352	1
all_pins[7]	transitions[0x1=>0x0]	89	1			T17	2		T40	1		T41	5