Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	55	73	57.03

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	55	73	57.03	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	398	1			T8	24		T172	18		T56	10
values[1]	484	1			T4	6		T44	10		T174	10
values[2]	514	1			T7	24		T12	12		T43	8
values[3]	304	1			T94	4		T91	10		T173	12
values[4]	546	1			T175	2		T176	12		T65	32
values[5]	402	1			T92	16		T55	14		T73	18
values[6]	396	1			T11	24		T93	6		T177	6
values[7]	216	1			T9	26		T64	8		T30	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	538	1			T8	24		T64	8		T172	18
values[1]	436	1			T7	24		T9	26		T26	20
values[2]	484	1			T92	16		T56	10		T89	6
values[3]	436	1			T94	4		T44	10		T66	6
values[4]	364	1			T43	8		T93	6		T31	12
values[5]	264	1			T67	34		T178	6		T179	18
values[6]	370	1			T12	12		T175	2		T180	2
values[7]	368	1			T4	6		T11	24		T62	26

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3224

1

T7

24

T4

6

T8

24

auto[1]

36

1

T56

4

T57

4

T58

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	55	73	57.03	55

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[values[4]]	0	1	1
[auto[0]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[3] , values[4] , values[5] , values[6]]	--	--	4
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2] , values[3] , values[4]]	--	--	3
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[2]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	7
[auto[1]]	[values[6] , values[7]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	12
[auto[1]]	[values[6] , values[7]]	[values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	104	1			T8	24		T172	18		T63	30
auto[0]	values[0]	values[1]	2	1			T181	2		-	-		-	-
auto[0]	values[0]	values[2]	74	1			T56	6		T89	6		T182	16
auto[0]	values[0]	values[3]	16	1			T183	4		T184	12		-	-
auto[0]	values[0]	values[4]	6	1			T185	4		T186	2		-	-
auto[0]	values[0]	values[5]	80	1			T179	18		T81	16		T187	6
auto[0]	values[0]	values[6]	32	1			T188	14		T189	14		T190	4
auto[0]	values[0]	values[7]	70	1			T57	22		T60	4		T191	24
auto[0]	values[1]	values[0]	6	1			T192	6		-	-		-	-
auto[0]	values[1]	values[1]	152	1			T174	10		T58	20		T193	2
auto[0]	values[1]	values[2]	90	1			T59	14		T194	12		T195	36
auto[0]	values[1]	values[3]	100	1			T44	10		T196	30		T197	14
auto[0]	values[1]	values[5]	60	1			T67	30		T198	6		T199	4
auto[0]	values[1]	values[6]	48	1			T200	4		T201	26		T202	18
auto[0]	values[1]	values[7]	22	1			T4	6		T203	4		T204	12
auto[0]	values[2]	values[0]	94	1			T29	30		T27	6		T205	14
auto[0]	values[2]	values[1]	90	1			T7	24		T26	20		T45	18
auto[0]	values[2]	values[2]	22	1			T206	4		T207	18		-	-
auto[0]	values[2]	values[3]	18	1			T66	6		T208	12		-	-
auto[0]	values[2]	values[4]	100	1			T43	8		T209	10		T210	26
auto[0]	values[2]	values[5]	66	1			T211	10		T212	18		T213	12
auto[0]	values[2]	values[6]	72	1			T12	12		T214	2		T68	10
auto[0]	values[2]	values[7]	48	1			T62	26		T75	8		T215	10
auto[0]	values[3]	values[0]	48	1			T173	12		T216	4		T217	32
auto[0]	values[3]	values[1]	10	1			T218	10		-	-		-	-
auto[0]	values[3]	values[2]	30	1			T219	12		T220	16		T221	2
auto[0]	values[3]	values[3]	70	1			T94	4		T222	2		T223	20
auto[0]	values[3]	values[4]	66	1			T91	10		T224	36		T225	20
auto[0]	values[3]	values[6]	30	1			T61	26		T226	4		-	-
auto[0]	values[3]	values[7]	48	1			T86	14		T96	22		T227	12
auto[0]	values[4]	values[0]	76	1			T228	2		T229	34		T230	12
auto[0]	values[4]	values[1]	78	1			T65	32		T231	34		T115	6
auto[0]	values[4]	values[2]	124	1			T232	16		T233	20		T234	12
auto[0]	values[4]	values[3]	74	1			T235	16		T236	20		T237	18
auto[0]	values[4]	values[4]	40	1			T176	12		T238	16		T239	12
auto[0]	values[4]	values[5]	8	1			T178	6		T240	2		-	-
auto[0]	values[4]	values[6]	102	1			T175	2		T241	8		T242	32
auto[0]	values[4]	values[7]	40	1			T69	16		T243	18		T169	2
auto[0]	values[5]	values[0]	90	1			T55	14		T244	2		T245	30
auto[0]	values[5]	values[1]	56	1			T78	18		T246	18		T247	20
auto[0]	values[5]	values[2]	84	1			T92	16		T248	18		T249	22
auto[0]	values[5]	values[3]	74	1			T250	26		T85	2		T108	12
auto[0]	values[5]	values[4]	30	1			T251	8		T252	20		T253	2
auto[0]	values[5]	values[5]	2	1			T254	2		-	-		-	-
auto[0]	values[5]	values[6]	26	1			T73	18		T255	8		-	-
auto[0]	values[5]	values[7]	40	1			T256	4		T257	32		T258	4
auto[0]	values[6]	values[0]	44	1			T177	6		T120	6		T259	32
auto[0]	values[6]	values[1]	16	1			T260	4		T167	6		T261	6
auto[0]	values[6]	values[2]	30	1			T28	16		T262	12		T263	2
auto[0]	values[6]	values[3]	82	1			T264	10		T265	6		T266	2
auto[0]	values[6]	values[4]	114	1			T93	6		T31	12		T90	4
auto[0]	values[6]	values[5]	36	1			T116	14		T267	2		T109	20
auto[0]	values[6]	values[6]	34	1			T180	2		T71	20		T88	6
auto[0]	values[6]	values[7]	36	1			T11	24		T268	2		T269	10
auto[0]	values[7]	values[0]	72	1			T64	8		T270	14		T271	24
auto[0]	values[7]	values[1]	30	1			T9	26		T272	4		-	-
auto[0]	values[7]	values[2]	24	1			T273	2		T274	2		T275	4
auto[0]	values[7]	values[3]	2	1			T276	2		-	-		-	-
auto[0]	values[7]	values[4]	8	1			T277	8		-	-		-	-
auto[0]	values[7]	values[5]	8	1			T278	8		-	-		-	-
auto[0]	values[7]	values[6]	18	1			T30	2		T72	14		T279	2
auto[0]	values[7]	values[7]	52	1			T113	10		T114	18		T280	14
auto[1]	values[0]	values[0]	2	1			T63	2		-	-		-	-
auto[1]	values[0]	values[2]	4	1			T56	4		-	-		-	-
auto[1]	values[0]	values[7]	8	1			T57	4		T70	4		-	-
auto[1]	values[1]	values[1]	2	1			T58	2		-	-		-	-
auto[1]	values[1]	values[5]	4	1			T67	4		-	-		-	-
auto[1]	values[2]	values[0]	2	1			T281	2		-	-		-	-
auto[1]	values[2]	values[6]	2	1			T68	2		-	-		-	-
auto[1]	values[3]	values[2]	2	1			T221	2		-	-		-	-
auto[1]	values[4]	values[7]	4	1			T69	4		-	-		-	-
auto[1]	values[6]	values[6]	4	1			T71	2		T282	2		-	-
auto[1]	values[7]	values[6]	2	1			T72	2		-	-		-	-