Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1335

1

T3

19

T14

8

T19

2

auto[1]

1323

1

T3

27

T14

5

T19

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665

1

T14

13

T19

3

T20

3

auto[1]

1993

1

T3

46

T21

8

T22

27

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2382

1

T3

46

T14

9

T19

2

auto[1]

276

1

T14

4

T19

1

T20

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	524	1			T3	10		T14	2		T19	1
valid[1]	536	1			T3	10		T14	3		T20	1
valid[2]	523	1			T3	9		T14	1		T20	1
valid[3]	547	1			T3	11		T14	4		T19	1
valid[4]	528	1			T3	6		T14	3		T19	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	41	1			T14	1		T50	1		T52	2
auto[0]	auto[0]	valid[0]	auto[1]	201	1			T3	3		T22	4		T23	7
auto[0]	auto[0]	valid[1]	auto[0]	39	1			T14	1		T51	1		T54	3
auto[0]	auto[0]	valid[1]	auto[1]	188	1			T3	5		T21	1		T22	1
auto[0]	auto[0]	valid[2]	auto[0]	40	1			T14	1		T54	1		T390	3
auto[0]	auto[0]	valid[2]	auto[1]	206	1			T3	6		T21	3		T22	4
auto[0]	auto[0]	valid[3]	auto[0]	31	1			T14	1		T19	1		T54	1
auto[0]	auto[0]	valid[3]	auto[1]	207	1			T3	4		T21	2		T22	3
auto[0]	auto[0]	valid[4]	auto[0]	49	1			T14	2		T54	3		T390	1
auto[0]	auto[0]	valid[4]	auto[1]	201	1			T3	1		T21	1		T22	1
auto[0]	auto[1]	valid[0]	auto[0]	38	1			T19	1		T52	1		T54	5
auto[0]	auto[1]	valid[0]	auto[1]	195	1			T3	7		T23	4		T104	2
auto[0]	auto[1]	valid[1]	auto[0]	37	1			T14	1		T20	1		T51	1
auto[0]	auto[1]	valid[1]	auto[1]	208	1			T3	5		T22	5		T23	4
auto[0]	auto[1]	valid[2]	auto[0]	41	1			T51	2		T52	1		T54	1
auto[0]	auto[1]	valid[2]	auto[1]	183	1			T3	3		T22	5		T23	8
auto[0]	auto[1]	valid[3]	auto[0]	32	1			T14	2		T51	1		T54	2
auto[0]	auto[1]	valid[3]	auto[1]	215	1			T3	7		T21	1		T23	7
auto[0]	auto[1]	valid[4]	auto[0]	41	1			T20	1		T51	1		T54	4
auto[0]	auto[1]	valid[4]	auto[1]	189	1			T3	5		T22	4		T23	9
auto[1]	auto[0]	valid[0]	auto[0]	24	1			T14	1		T51	1		T53	1
auto[1]	auto[0]	valid[1]	auto[0]	35	1			T51	1		T54	4		T384	2
auto[1]	auto[0]	valid[2]	auto[0]	20	1			T20	1		T51	3		T390	1
auto[1]	auto[0]	valid[3]	auto[0]	27	1			T14	1		T51	1		T385	3
auto[1]	auto[0]	valid[4]	auto[0]	26	1			T19	1		T52	1		T405	1
auto[1]	auto[1]	valid[0]	auto[0]	25	1			T52	1		T54	1		T390	2
auto[1]	auto[1]	valid[1]	auto[0]	29	1			T14	1		T390	1		T385	1
auto[1]	auto[1]	valid[2]	auto[0]	33	1			T51	1		T54	1		T390	2
auto[1]	auto[1]	valid[3]	auto[0]	35	1			T51	1		T54	1		T396	1
auto[1]	auto[1]	valid[4]	auto[0]	22	1			T14	1		T384	1		T103	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal