Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15829

1

T1

5

T13

17

T14

404

auto[1]

20140

1

T3

578

T19

14

T21

115

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30174

1

T3

578

T13

8

T14

282

auto[1]

5795

1

T1

5

T13

9

T14

122

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	18752	1			T1	2		T3	296		T13	10
others[1]	3012	1			T1	1		T3	45		T13	1
others[2]	2952	1			T1	1		T3	55		T13	1
others[3]	3341	1			T3	62		T13	4		T14	38
interest[1]	2021	1			T3	38		T13	1		T14	28
interest[4]	12349	1			T1	1		T3	197		T13	7
interest[64]	5891	1			T1	1		T3	82		T14	62

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5196	1			T13	5		T14	155		T19	14
auto[0]	auto[0]	others[1]	821	1			T14	21		T19	1		T20	7
auto[0]	auto[0]	others[2]	845	1			T14	22		T20	4		T49	1
auto[0]	auto[0]	others[3]	910	1			T13	2		T14	27		T19	3
auto[0]	auto[0]	interest[1]	582	1			T13	1		T14	20		T20	1
auto[0]	auto[0]	interest[4]	3331	1			T13	3		T14	99		T19	10
auto[0]	auto[0]	interest[64]	1680	1			T14	37		T19	7		T20	14
auto[0]	auto[1]	others[0]	10531	1			T3	296		T19	8		T21	65
auto[0]	auto[1]	others[1]	1725	1			T3	45		T19	1		T21	7
auto[0]	auto[1]	others[2]	1637	1			T3	55		T19	2		T21	5
auto[0]	auto[1]	others[3]	1920	1			T3	62		T19	1		T21	13
auto[0]	auto[1]	interest[1]	1121	1			T3	38		T19	1		T21	3
auto[0]	auto[1]	interest[4]	7000	1			T3	197		T19	6		T21	37
auto[0]	auto[1]	interest[64]	3206	1			T3	82		T19	1		T21	22
auto[1]	auto[0]	others[0]	3025	1			T1	2		T13	5		T14	57
auto[1]	auto[0]	others[1]	466	1			T1	1		T13	1		T14	13
auto[1]	auto[0]	others[2]	470	1			T1	1		T13	1		T14	8
auto[1]	auto[0]	others[3]	511	1			T13	2		T14	11		T19	3
auto[1]	auto[0]	interest[1]	318	1			T14	8		T19	3		T20	4
auto[1]	auto[0]	interest[4]	2018	1			T1	1		T13	4		T14	37
auto[1]	auto[0]	interest[64]	1005	1			T1	1		T14	25		T19	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal