Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	515	1			T17	17		T40	14		T41	20
all_values[1]	515	1			T17	17		T40	14		T41	20
all_values[2]	515	1			T17	17		T40	14		T41	20
all_values[3]	515	1			T17	17		T40	14		T41	20
all_values[4]	515	1			T17	17		T40	14		T41	20
all_values[5]	515	1			T17	17		T40	14		T41	20
all_values[6]	515	1			T17	17		T40	14		T41	20
all_values[7]	515	1			T17	17		T40	14		T41	20

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2200

1

T17

59

T40

56

T41

83

auto[1]

1920

1

T17

77

T40

56

T41

77

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1703

1

T17

53

T40

43

T41

59

auto[1]

2417

1

T17

83

T40

69

T41

101

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2361

1

T17

70

T40

60

T41

85

auto[1]

1759

1

T17

66

T40

52

T41

75

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	101	1			T17	1		T40	4		T41	1
all_values[0]	auto[0]	auto[0]	auto[1]	60	1			T17	3		T41	2		T352	2
all_values[0]	auto[0]	auto[1]	auto[0]	90	1			T17	5		T40	5		T41	1
all_values[0]	auto[0]	auto[1]	auto[1]	51	1			T17	1		T40	1		T41	5
all_values[0]	auto[1]	auto[0]	auto[1]	116	1			T17	4		T40	2		T41	5
all_values[0]	auto[1]	auto[1]	auto[1]	97	1			T17	3		T40	2		T41	6
all_values[1]	auto[0]	auto[0]	auto[0]	114	1			T41	4		T352	2		T353	4
all_values[1]	auto[0]	auto[0]	auto[1]	37	1			T17	1		T40	1		T41	1
all_values[1]	auto[0]	auto[1]	auto[0]	96	1			T17	4		T40	3		T41	8
all_values[1]	auto[0]	auto[1]	auto[1]	52	1			T17	4		T40	4		T352	2
all_values[1]	auto[1]	auto[0]	auto[1]	122	1			T17	4		T40	1		T41	5
all_values[1]	auto[1]	auto[1]	auto[1]	94	1			T17	4		T40	5		T41	2
all_values[2]	auto[0]	auto[0]	auto[0]	92	1			T17	1		T40	1		T41	4
all_values[2]	auto[0]	auto[0]	auto[1]	45	1			T40	1		T41	4		T352	2
all_values[2]	auto[0]	auto[1]	auto[0]	91	1			T17	4		T40	7		T41	2
all_values[2]	auto[0]	auto[1]	auto[1]	64	1			T17	3		T352	2		T353	1
all_values[2]	auto[1]	auto[0]	auto[1]	142	1			T17	4		T40	4		T41	10
all_values[2]	auto[1]	auto[1]	auto[1]	81	1			T17	5		T40	1		T352	2
all_values[3]	auto[0]	auto[0]	auto[0]	115	1			T17	5		T40	4		T41	9
all_values[3]	auto[0]	auto[0]	auto[1]	47	1			T17	1		T40	3		T41	1
all_values[3]	auto[0]	auto[1]	auto[0]	90	1			T41	4		T352	2		T160	3
all_values[3]	auto[0]	auto[1]	auto[1]	29	1			T17	1		T354	1		T355	2
all_values[3]	auto[1]	auto[0]	auto[1]	127	1			T17	6		T40	4		T41	4
all_values[3]	auto[1]	auto[1]	auto[1]	107	1			T17	4		T40	3		T41	2
all_values[4]	auto[0]	auto[0]	auto[0]	94	1			T17	2		T40	2		T41	5
all_values[4]	auto[0]	auto[0]	auto[1]	54	1			T40	2		T41	3		T352	2
all_values[4]	auto[0]	auto[1]	auto[0]	91	1			T17	3		T40	1		T41	3
all_values[4]	auto[0]	auto[1]	auto[1]	45	1			T40	1		T41	2		T353	2
all_values[4]	auto[1]	auto[0]	auto[1]	115	1			T17	2		T40	5		T41	3
all_values[4]	auto[1]	auto[1]	auto[1]	116	1			T17	10		T40	3		T41	4
all_values[5]	auto[0]	auto[0]	auto[0]	157	1			T17	4		T40	3		T41	4
all_values[5]	auto[0]	auto[1]	auto[0]	147	1			T17	5		T40	5		T41	7
all_values[5]	auto[1]	auto[0]	auto[1]	125	1			T17	4		T40	4		T41	6
all_values[5]	auto[1]	auto[1]	auto[1]	86	1			T17	4		T40	2		T41	3
all_values[6]	auto[0]	auto[0]	auto[0]	115	1			T17	4		T40	4		T41	2
all_values[6]	auto[0]	auto[0]	auto[1]	48	1			T40	1		T352	2		T353	4
all_values[6]	auto[0]	auto[1]	auto[0]	93	1			T17	4		T41	3		T352	4
all_values[6]	auto[0]	auto[1]	auto[1]	46	1			T17	2		T40	1		T41	3
all_values[6]	auto[1]	auto[0]	auto[1]	106	1			T17	4		T40	2		T41	4
all_values[6]	auto[1]	auto[1]	auto[1]	107	1			T17	3		T40	6		T41	8
all_values[7]	auto[0]	auto[0]	auto[0]	131	1			T17	5		T40	2		T352	9
all_values[7]	auto[0]	auto[0]	auto[1]	36	1			T40	2		T41	2		T353	2
all_values[7]	auto[0]	auto[1]	auto[0]	86	1			T17	6		T40	2		T41	2
all_values[7]	auto[0]	auto[1]	auto[1]	44	1			T17	1		T41	3		T160	2
all_values[7]	auto[1]	auto[0]	auto[1]	101	1			T17	4		T40	4		T41	4
all_values[7]	auto[1]	auto[1]	auto[1]	117	1			T17	1		T40	4		T41	9

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal