Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	303425	1			T1	1668		T2	1164		T3	1
all_values[1]	303425	1			T1	1668		T2	1164		T3	1
all_values[2]	303425	1			T1	1668		T2	1164		T3	1
all_values[3]	303425	1			T1	1668		T2	1164		T3	1
all_values[4]	303425	1			T1	1668		T2	1164		T3	1
all_values[5]	303425	1			T1	1668		T2	1164		T3	1
all_values[6]	303425	1			T1	1668		T2	1164		T3	1
all_values[7]	303425	1			T1	1668		T2	1164		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425241

1

T1

13344

T2

9312

T3

8

auto[1]

2159

1

T21

79

T38

94

T39

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425415

1

T1

13344

T2

9306

T3

8

auto[1]

1985

1

T2

6

T13

13

T21

75

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	303015	1			T1	1668		T2	1164		T3	1
all_values[0]	auto[0]	auto[1]	119	1			T21	7		T38	3		T39	1
all_values[0]	auto[1]	auto[0]	183	1			T21	7		T38	8		T39	3
all_values[0]	auto[1]	auto[1]	108	1			T21	2		T38	2		T39	4
all_values[1]	auto[0]	auto[0]	303034	1			T1	1668		T2	1164		T3	1
all_values[1]	auto[0]	auto[1]	112	1			T21	5		T38	2		T39	1
all_values[1]	auto[1]	auto[0]	178	1			T21	3		T38	7		T39	4
all_values[1]	auto[1]	auto[1]	101	1			T21	6		T38	8		T39	1
all_values[2]	auto[0]	auto[0]	303059	1			T1	1668		T2	1164		T3	1
all_values[2]	auto[0]	auto[1]	117	1			T21	7		T38	3		T39	3
all_values[2]	auto[1]	auto[0]	155	1			T21	3		T38	6		T39	2
all_values[2]	auto[1]	auto[1]	94	1			T21	7		T38	6		T39	1
all_values[3]	auto[0]	auto[0]	303026	1			T1	1668		T2	1164		T3	1
all_values[3]	auto[0]	auto[1]	142	1			T21	3		T38	1		T294	15
all_values[3]	auto[1]	auto[0]	159	1			T21	8		T38	12		T39	5
all_values[3]	auto[1]	auto[1]	98	1			T21	4		T38	4		T39	2
all_values[4]	auto[0]	auto[0]	303028	1			T1	1668		T2	1164		T3	1
all_values[4]	auto[0]	auto[1]	141	1			T21	2		T38	4		T305	7
all_values[4]	auto[1]	auto[0]	160	1			T21	7		T38	8		T39	2
all_values[4]	auto[1]	auto[1]	96	1			T21	2		T38	4		T39	1
all_values[5]	auto[0]	auto[0]	302852	1			T1	1668		T2	1158		T3	1
all_values[5]	auto[0]	auto[1]	301	1			T2	6		T13	13		T21	3
all_values[5]	auto[1]	auto[0]	165	1			T21	3		T38	6		T39	4
all_values[5]	auto[1]	auto[1]	107	1			T21	6		T38	3		T39	1
all_values[6]	auto[0]	auto[0]	303027	1			T1	1668		T2	1164		T3	1
all_values[6]	auto[0]	auto[1]	119	1			T21	7		T38	2		T39	2
all_values[6]	auto[1]	auto[0]	167	1			T21	3		T38	10		T39	5
all_values[6]	auto[1]	auto[1]	112	1			T21	3		T38	4		T39	2
all_values[7]	auto[0]	auto[0]	303026	1			T1	1668		T2	1164		T3	1
all_values[7]	auto[0]	auto[1]	123	1			T21	5		T38	8		T39	2
all_values[7]	auto[1]	auto[0]	181	1			T21	9		T38	4		T40	4
all_values[7]	auto[1]	auto[1]	95	1			T21	6		T38	2		T40	12