Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	32	52	61.90

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	954	1			T1	8		T6	2		T8	8
auto[SpiFlashAddrCfg]	870	1			T1	4		T8	2		T9	10
auto[SpiFlashAddr3b]	1088	1			T1	6		T8	10		T9	6
auto[SpiFlashAddr4b]	935	1			T1	8		T8	10		T9	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3051

1

T1

26

T6

2

T8

30

auto[1]

796

1

T11

10

T62

26

T59

24

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2010

1

T1

10

T6

2

T8

22

auto[1]

1837

1

T1

16

T8

8

T9

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1371	1			T1	8		T6	2		T8	12
values[1]	99	1			T8	4		T59	4		T61	4
values[2]	170	1			T8	2		T11	2		T47	2
values[3]	203	1			T1	6		T62	10		T88	4
values[4]	165	1			T9	2		T11	2		T47	2
values[5]	246	1			T9	2		T10	6		T11	2
values[6]	225	1			T1	2		T10	4		T62	4
values[7]	168	1			T1	2		T8	2		T10	4
values[8]	1200	1			T1	8		T8	10		T9	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3188

1

T1

26

T6

2

T8

30

auto[1]

659

1

T80

1

T81

16

T291

15

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3729

1

T1

26

T6

2

T8

30

write

118

1

T59

12

T60

2

T61

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1905

1

T1

18

T6

2

T8

14

valids[0x1]

1942

1

T1

8

T8

16

T9

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	142	1			T1	2		T62	2		T42	6
internal_process_ops[0x5a]	168	1			T9	2		T62	2		T42	2
internal_process_ops[0x05]	188	1			T1	2		T42	2		T66	4
internal_process_ops[0x35]	182	1			T1	2		T8	8		T42	2
internal_process_ops[0x15]	162	1			T60	2		T65	2		T79	4
internal_process_ops[0x03]	311	1			T8	2		T9	8		T76	2
internal_process_ops[0x0b]	217	1			T1	2		T9	2		T62	2
internal_process_ops[0x3b]	284	1			T1	6		T9	2		T10	2
internal_process_ops[0x6b]	281	1			T1	2		T9	2		T11	2
internal_process_ops[0xbb]	281	1			T62	2		T47	2		T61	2
internal_process_ops[0xeb]	317	1			T1	2		T8	2		T9	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3795

1

T1

26

T6

2

T8

30

auto[1]

52

1

T59

12

T60

2

T61

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3847

1

T1

26

T6

2

T8

30

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

742

1

T1

8

T6

2

T8

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

188

1

T62

2

T59

4

T60

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

454

1

T1

4

T8

2

T9

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

158

1

T11

4

T62

2

T59

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

640

1

T1

6

T8

10

T9

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

218

1

T11

4

T62

10

T76

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

490

1

T1

8

T8

10

T9

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

180

1

T11

2

T62

12

T59

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T67

2

T185

2

T203

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

8

1

T72

4

T176

4

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

16

1

T27

6

T279

6

T215

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

24

1

T60

2

T61

6

T68

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

10

1

T274

2

T226

2

T235

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

10

1

T59

10

-

-

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

24

1

T198

4

T217

4

T242

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

10

1

T59

2

T70

2

T73

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

218

1

T81

2

T291

11

T82

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

210

1

T81

7

T291

4

T119

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

231

1

T80

1

T81

7

T119

6

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	220	1			T1	2		T6	2		T10	8
auto[0]	values[0]	valids[0x1]	1070	1			T1	6		T8	12		T9	4
auto[0]	values[1]	valids[0x1]	92	1			T8	4		T59	4		T61	4
auto[0]	values[2]	valids[0x0]	110	1			T8	2		T11	2		T47	2
auto[0]	values[2]	valids[0x1]	48	1			T42	2		T27	2		T28	2
auto[0]	values[3]	valids[0x0]	110	1			T1	6		T62	10		T88	4
auto[0]	values[3]	valids[0x1]	44	1			T78	2		T185	2		T79	2
auto[0]	values[4]	valids[0x0]	96	1			T9	2		T47	2		T61	2
auto[0]	values[4]	valids[0x1]	46	1			T11	2		T77	2		T88	2
auto[0]	values[5]	valids[0x0]	114	1			T9	2		T10	6		T12	2
auto[0]	values[5]	valids[0x1]	62	1			T11	2		T66	8		T191	2
auto[0]	values[6]	valids[0x0]	96	1			T1	2		T10	4		T62	4
auto[0]	values[6]	valids[0x1]	46	1			T88	4		T191	2		T68	4
auto[0]	values[7]	valids[0x0]	76	1			T1	2		T8	2		T62	2
auto[0]	values[7]	valids[0x1]	34	1			T10	4		T63	2		T185	4
auto[0]	values[8]	valids[0x0]	644	1			T1	6		T8	10		T9	2
auto[0]	values[8]	valids[0x1]	280	1			T1	2		T9	8		T10	6
auto[1]	values[0]	valids[0x1]	81	1			T81	6		T82	2		T292	5
auto[1]	values[1]	valids[0x1]	7	1			T293	7		-	-		-	-
auto[1]	values[2]	valids[0x0]	3	1			T294	3		-	-		-	-
auto[1]	values[2]	valids[0x1]	9	1			T120	5		T295	4		-	-
auto[1]	values[3]	valids[0x0]	36	1			T119	2		T82	6		T296	5
auto[1]	values[3]	valids[0x1]	13	1			T297	5		T298	5		T299	3
auto[1]	values[4]	valids[0x0]	19	1			T297	6		T294	4		T300	6
auto[1]	values[4]	valids[0x1]	4	1			T301	4		-	-		-	-
auto[1]	values[5]	valids[0x0]	51	1			T297	3		T295	3		T299	3
auto[1]	values[5]	valids[0x1]	19	1			T292	7		T302	5		T303	7
auto[1]	values[6]	valids[0x0]	63	1			T81	1		T119	4		T82	8
auto[1]	values[6]	valids[0x1]	20	1			T119	6		T304	1		T305	5
auto[1]	values[7]	valids[0x0]	36	1			T81	2		T82	4		T306	5
auto[1]	values[7]	valids[0x1]	22	1			T291	4		T293	1		T307	7
auto[1]	values[8]	valids[0x0]	231	1			T80	1		T81	7		T291	6
auto[1]	values[8]	valids[0x1]	45	1			T291	5		T296	5		T308	7