Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1106547 1 T1 259 T6 6 T8 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1011087 1 T1 1 T6 6 T8 1
auto[1] 95460 1 T1 258 T42 5994 T43 256


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 249381 1 T1 259 T8 1 T9 2105
auto[524288:1048575] 110787 1 T9 1181 T47 239 T83 2
auto[1048576:1572863] 122321 1 T9 1737 T26 166 T86 55
auto[1572864:2097151] 109601 1 T9 1204 T47 3716 T83 95
auto[2097152:2621439] 130158 1 T9 3 T47 1 T86 50
auto[2621440:3145727] 139849 1 T9 630 T26 49 T86 33
auto[3145728:3670015] 116504 1 T6 6 T9 566 T47 2
auto[3670016:4194303] 127946 1 T9 1042 T47 2326 T26 124


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 107346 1 T1 259 T6 2 T8 1
auto[1] 999201 1 T6 4 T9 8290 T47 7185


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1106547 1 T1 259 T6 6 T8 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 175388 1 T1 1 T8 1 T9 2105
auto[0] auto[0] auto[0:524287] auto[1] 73993 1 T1 258 T42 5994 T43 256
auto[0] auto[0] auto[524288:1048575] auto[0] 109519 1 T9 1181 T47 239 T83 2
auto[0] auto[0] auto[524288:1048575] auto[1] 1268 1 T106 675 T182 131 T183 127
auto[0] auto[0] auto[1048576:1572863] auto[0] 120973 1 T9 1737 T26 166 T86 55
auto[0] auto[0] auto[1048576:1572863] auto[1] 1348 1 T106 49 T182 1 T183 757
auto[0] auto[0] auto[1572864:2097151] auto[0] 107844 1 T9 1204 T47 3716 T83 95
auto[0] auto[0] auto[1572864:2097151] auto[1] 1757 1 T106 1193 T182 129 T183 1
auto[0] auto[0] auto[2097152:2621439] auto[0] 127073 1 T9 3 T47 1 T86 50
auto[0] auto[0] auto[2097152:2621439] auto[1] 3085 1 T106 680 T182 103 T183 410
auto[0] auto[0] auto[2621440:3145727] auto[0] 135681 1 T9 630 T26 49 T86 33
auto[0] auto[0] auto[2621440:3145727] auto[1] 4168 1 T106 812 T182 2260 T183 5
auto[0] auto[0] auto[3145728:3670015] auto[0] 111123 1 T6 6 T9 566 T47 2
auto[0] auto[0] auto[3145728:3670015] auto[1] 5381 1 T184 1165 T106 661 T182 2160
auto[0] auto[0] auto[3670016:4194303] auto[0] 123486 1 T9 1042 T47 2326 T26 124
auto[0] auto[0] auto[3670016:4194303] auto[1] 4460 1 T106 1218 T182 919 T183 1156


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 107346 1 T1 259 T6 2 T8 1
auto[0] auto[0] auto[1] 999201 1 T6 4 T9 8290 T47 7185

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%