Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	33	95	74.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	33	95	74.22	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2392

1

T1

26

T6

2

T8

30

auto[1]

796

1

T11

10

T62

26

T59

24

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	348	1			T66	22		T88	32		T264	2
values[1]	458	1			T12	2		T59	24		T63	16
values[2]	468	1			T8	30		T62	26		T28	34
values[3]	384	1			T6	2		T9	18		T77	4
values[4]	260	1			T1	26		T61	32		T89	2
values[5]	352	1			T76	14		T60	12		T191	16
values[6]	502	1			T10	28		T11	10		T65	10
values[7]	416	1			T47	4		T42	28		T43	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	266	1			T89	2		T27	18		T109	8
values[1]	260	1			T87	4		T78	12		T45	12
values[2]	326	1			T10	28		T11	10		T88	32
values[3]	428	1			T47	4		T77	4		T190	20
values[4]	288	1			T6	2		T9	18		T79	16
values[5]	524	1			T62	26		T59	24		T60	12
values[6]	610	1			T1	26		T8	30		T12	2
values[7]	486	1			T76	14		T26	4		T86	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	33	95	74.22	33

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[values[4]]	0	1	1
[auto[0]]	[values[3]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[0]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[2]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[1]]	0	1	1
[auto[1]]	[values[6]]	[values[1]]	0	1	1
[auto[1]]	[values[6]]	[values[3]]	0	1	1
[auto[1]]	[values[6]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[7]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	24	1			T289	24		-	-		-	-
auto[0]	values[0]	values[1]	4	1			T309	4		-	-		-	-
auto[0]	values[0]	values[2]	22	1			T238	12		T209	2		T310	8
auto[0]	values[0]	values[3]	18	1			T242	2		T248	16		-	-
auto[0]	values[0]	values[4]	2	1			T246	2		-	-		-	-
auto[0]	values[0]	values[5]	86	1			T44	18		T254	6		T275	14
auto[0]	values[0]	values[6]	42	1			T264	2		T46	6		T107	16
auto[0]	values[0]	values[7]	46	1			T67	26		T263	2		T233	10
auto[0]	values[1]	values[0]	16	1			T231	8		T213	8		-	-
auto[0]	values[1]	values[1]	52	1			T311	28		T244	6		T230	18
auto[0]	values[1]	values[2]	36	1			T285	14		T312	2		T313	18
auto[0]	values[1]	values[3]	76	1			T241	4		T183	12		T25	14
auto[0]	values[1]	values[5]	36	1			T201	6		T314	2		T315	28
auto[0]	values[1]	values[6]	54	1			T12	2		T137	6		T185	34
auto[0]	values[1]	values[7]	52	1			T86	4		T114	22		T177	26
auto[0]	values[2]	values[0]	28	1			T276	14		T173	14		-	-
auto[0]	values[2]	values[1]	20	1			T220	6		T199	14		-	-
auto[0]	values[2]	values[2]	2	1			T316	2		-	-		-	-
auto[0]	values[2]	values[3]	62	1			T28	34		T258	12		T317	14
auto[0]	values[2]	values[4]	16	1			T243	2		T239	2		T318	8
auto[0]	values[2]	values[5]	38	1			T235	22		T319	16		-	-
auto[0]	values[2]	values[6]	78	1			T8	30		T186	6		T320	28
auto[0]	values[2]	values[7]	78	1			T215	6		T255	10		T321	12
auto[0]	values[3]	values[0]	20	1			T322	20		-	-		-	-
auto[0]	values[3]	values[1]	36	1			T323	2		T324	34		-	-
auto[0]	values[3]	values[3]	22	1			T265	22		-	-		-	-
auto[0]	values[3]	values[4]	20	1			T6	2		T9	18		-	-
auto[0]	values[3]	values[5]	96	1			T279	28		T218	14		T325	30
auto[0]	values[3]	values[6]	10	1			T253	10		-	-		-	-
auto[0]	values[3]	values[7]	80	1			T26	4		T326	26		T195	16
auto[0]	values[4]	values[0]	34	1			T89	2		T27	18		T327	14
auto[0]	values[4]	values[1]	4	1			T328	4		-	-		-	-
auto[0]	values[4]	values[2]	52	1			T189	8		T202	34		T329	10
auto[0]	values[4]	values[3]	14	1			T266	6		T284	8		-	-
auto[0]	values[4]	values[4]	30	1			T229	14		T330	12		T331	4
auto[0]	values[4]	values[5]	10	1			T210	10		-	-		-	-
auto[0]	values[4]	values[6]	42	1			T1	26		T332	16		-	-
auto[0]	values[4]	values[7]	36	1			T184	2		T245	16		T333	12
auto[0]	values[5]	values[0]	40	1			T261	6		T334	18		T219	8
auto[0]	values[5]	values[1]	6	1			T335	6		-	-		-	-
auto[0]	values[5]	values[2]	12	1			T192	12		-	-		-	-
auto[0]	values[5]	values[3]	28	1			T336	28		-	-		-	-
auto[0]	values[5]	values[4]	12	1			T221	12		-	-		-	-
auto[0]	values[5]	values[5]	10	1			T225	10		-	-		-	-
auto[0]	values[5]	values[6]	34	1			T249	10		T337	20		T338	4
auto[0]	values[5]	values[7]	58	1			T24	2		T91	14		T339	14
auto[0]	values[6]	values[0]	4	1			T340	4		-	-		-	-
auto[0]	values[6]	values[1]	52	1			T78	12		T45	12		T228	28
auto[0]	values[6]	values[2]	52	1			T10	28		T193	24		-	-
auto[0]	values[6]	values[3]	98	1			T198	16		T106	16		T113	12
auto[0]	values[6]	values[4]	80	1			T217	36		T287	4		T282	2
auto[0]	values[6]	values[5]	70	1			T65	10		T90	20		T341	28
auto[0]	values[6]	values[6]	42	1			T203	20		T342	22		-	-
auto[0]	values[6]	values[7]	26	1			T252	16		T182	10		-	-
auto[0]	values[7]	values[0]	12	1			T109	8		T204	4		-	-
auto[0]	values[7]	values[1]	68	1			T87	4		T223	16		T286	30
auto[0]	values[7]	values[2]	52	1			T343	2		T268	6		T234	4
auto[0]	values[7]	values[3]	4	1			T47	4		-	-		-	-
auto[0]	values[7]	values[4]	50	1			T250	24		T278	26		-	-
auto[0]	values[7]	values[5]	74	1			T240	10		T344	10		T214	28
auto[0]	values[7]	values[6]	106	1			T42	28		T43	10		T194	8
auto[0]	values[7]	values[7]	8	1			T272	4		T345	4		-	-
auto[1]	values[0]	values[2]	54	1			T88	32		T232	22		-	-
auto[1]	values[0]	values[5]	4	1			T197	4		-	-		-	-
auto[1]	values[0]	values[6]	46	1			T66	22		T71	24		-	-
auto[1]	values[1]	values[0]	40	1			T200	12		T216	28		-	-
auto[1]	values[1]	values[3]	2	1			T207	2		-	-		-	-
auto[1]	values[1]	values[4]	2	1			T247	2		-	-		-	-
auto[1]	values[1]	values[5]	48	1			T59	24		T63	16		T70	8
auto[1]	values[1]	values[6]	24	1			T288	6		T176	18		-	-
auto[1]	values[1]	values[7]	20	1			T74	20		-	-		-	-
auto[1]	values[2]	values[0]	18	1			T273	18		-	-		-	-
auto[1]	values[2]	values[3]	28	1			T206	28		-	-		-	-
auto[1]	values[2]	values[4]	34	1			T346	34		-	-		-	-
auto[1]	values[2]	values[5]	40	1			T62	26		T69	14		-	-
auto[1]	values[2]	values[6]	26	1			T259	26		-	-		-	-
auto[1]	values[3]	values[1]	2	1			T251	2		-	-		-	-
auto[1]	values[3]	values[2]	2	1			T205	2		-	-		-	-
auto[1]	values[3]	values[3]	60	1			T77	4		T190	20		T72	20
auto[1]	values[3]	values[6]	36	1			T64	28		T281	8		-	-
auto[1]	values[4]	values[6]	38	1			T61	32		T347	6		-	-
auto[1]	values[5]	values[0]	2	1			T290	2		-	-		-	-
auto[1]	values[5]	values[2]	16	1			T191	16		-	-		-	-
auto[1]	values[5]	values[3]	16	1			T348	16		-	-		-	-
auto[1]	values[5]	values[4]	6	1			T187	6		-	-		-	-
auto[1]	values[5]	values[5]	12	1			T60	12		-	-		-	-
auto[1]	values[5]	values[6]	32	1			T68	26		T349	6		-	-
auto[1]	values[5]	values[7]	68	1			T76	14		T188	12		T73	30
auto[1]	values[6]	values[0]	18	1			T350	18		-	-		-	-
auto[1]	values[6]	values[2]	10	1			T11	10		-	-		-	-
auto[1]	values[6]	values[4]	36	1			T79	16		T283	20		-	-
auto[1]	values[6]	values[7]	14	1			T211	14		-	-		-	-
auto[1]	values[7]	values[0]	10	1			T351	10		-	-		-	-
auto[1]	values[7]	values[1]	16	1			T227	16		-	-		-	-
auto[1]	values[7]	values[2]	16	1			T352	16		-	-		-	-