Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 66 0 66 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_filtered 2 0 2 100.00 100 1 1 2
cp_opcode 64 0 64 100.00 100 1 1 64


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_filtered

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_filtered

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1594 1 T1 13 T6 1 T8 15
auto[1] 2253 1 T1 13 T6 1 T8 15



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 64 0 64 100.00


Automatically Generated Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] 323 1 T8 2 T9 8 T76 10
auto[4:7] 228 1 T1 2 T6 2 T42 2
auto[8:11] 239 1 T1 2 T9 2 T62 2
auto[12:15] 24 1 T10 4 T42 4 T190 4
auto[16:19] 4 1 T226 4 - - - -
auto[20:23] 170 1 T60 2 T65 2 T185 2
auto[24:27] 16 1 T193 2 T339 2 T320 2
auto[28:31] 30 1 T63 2 T67 2 T185 4
auto[32:35] 34 1 T194 2 T198 4 T241 2
auto[36:39] 4 1 T269 2 T222 2 - -
auto[40:43] 16 1 T28 4 T73 4 T237 4
auto[44:47] 26 1 T66 8 T192 4 T217 2
auto[48:51] 24 1 T63 2 T27 6 T223 2
auto[52:55] 190 1 T1 2 T8 8 T42 2
auto[56:59] 286 1 T1 6 T9 2 T10 2
auto[60:63] 20 1 T1 2 T62 6 T188 2
auto[64:67] 22 1 T59 10 T343 2 T227 2
auto[68:71] 10 1 T320 4 T220 2 T283 2
auto[72:75] 28 1 T76 2 T339 4 T72 6
auto[76:79] 12 1 T8 2 T61 2 T206 2
auto[80:83] 14 1 T198 4 T64 6 T320 4
auto[84:87] 20 1 T8 6 T65 2 T200 2
auto[88:91] 180 1 T9 2 T62 2 T42 2
auto[92:95] 26 1 T61 6 T27 2 T28 2
auto[96:99] 28 1 T42 4 T68 6 T206 6
auto[100:103] 30 1 T11 2 T67 10 T227 2
auto[104:107] 289 1 T1 2 T9 2 T10 6
auto[108:111] 26 1 T1 2 T61 4 T67 2
auto[112:115] 16 1 T191 2 T223 4 T341 4
auto[116:119] 8 1 T66 4 T70 2 T287 2
auto[120:123] 24 1 T188 8 T43 2 T78 2
auto[124:127] 30 1 T8 2 T88 2 T200 2
auto[128:131] 26 1 T88 2 T194 2 T198 2
auto[132:135] 24 1 T60 2 T190 6 T67 2
auto[136:139] 26 1 T11 2 T191 4 T223 2
auto[140:143] 14 1 T1 2 T326 4 T198 2
auto[144:147] 18 1 T10 4 T278 4 T375 4
auto[148:151] 30 1 T28 4 T227 4 T218 6
auto[152:155] 16 1 T275 2 T248 2 T74 4
auto[156:159] 160 1 T1 2 T62 2 T42 6
auto[160:163] 14 1 T78 2 T185 2 T198 2
auto[164:167] 24 1 T8 4 T69 2 T203 2
auto[168:171] 34 1 T65 2 T88 4 T68 6
auto[172:175] 26 1 T88 4 T69 4 T217 4
auto[176:179] 12 1 T67 2 T279 2 T202 4
auto[180:183] 62 1 T26 2 T27 2 T28 4
auto[184:187] 303 1 T62 4 T47 2 T61 2
auto[188:191] 14 1 T341 2 T228 4 T202 2
auto[192:195] 20 1 T8 4 T12 2 T191 2
auto[196:199] 6 1 T10 2 T249 2 T283 2
auto[200:203] 24 1 T11 2 T63 2 T193 2
auto[204:207] 22 1 T66 2 T68 2 T79 2
auto[208:211] 8 1 T255 2 T250 2 T226 2
auto[212:215] 18 1 T341 2 T324 10 T214 2
auto[216:219] 26 1 T10 4 T62 4 T59 4
auto[220:223] 18 1 T59 6 T77 2 T69 2
auto[224:227] 22 1 T61 2 T188 2 T275 2
auto[228:231] 14 1 T67 6 T268 2 T376 2
auto[232:235] 379 1 T1 4 T8 2 T9 2
auto[236:239] 24 1 T59 2 T65 2 T27 2
auto[240:243] 14 1 T279 6 T195 2 T317 4
auto[244:247] 10 1 T194 2 T320 4 T240 2
auto[248:251] 22 1 T43 4 T28 2 T279 2
auto[252:255] 20 1 T68 4 T339 2 T259 4



Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_opcodecp_filteredCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] auto[0] 97 1 T8 1 T9 4 T76 5
auto[0:3] auto[1] 226 1 T8 1 T9 4 T76 5
auto[4:7] auto[0] 114 1 T1 1 T6 1 T42 1
auto[4:7] auto[1] 114 1 T1 1 T6 1 T42 1
auto[8:11] auto[0] 74 1 T1 1 T9 1 T62 1
auto[8:11] auto[1] 165 1 T1 1 T9 1 T62 1
auto[12:15] auto[0] 12 1 T10 2 T42 2 T190 2
auto[12:15] auto[1] 12 1 T10 2 T42 2 T190 2
auto[16:19] auto[0] 2 1 T226 2 - - - -
auto[16:19] auto[1] 2 1 T226 2 - - - -
auto[20:23] auto[0] 85 1 T60 1 T65 1 T185 1
auto[20:23] auto[1] 85 1 T60 1 T65 1 T185 1
auto[24:27] auto[0] 8 1 T193 1 T339 1 T320 1
auto[24:27] auto[1] 8 1 T193 1 T339 1 T320 1
auto[28:31] auto[0] 15 1 T63 1 T67 1 T185 2
auto[28:31] auto[1] 15 1 T63 1 T67 1 T185 2
auto[32:35] auto[0] 17 1 T194 1 T198 2 T241 1
auto[32:35] auto[1] 17 1 T194 1 T198 2 T241 1
auto[36:39] auto[0] 2 1 T269 1 T222 1 - -
auto[36:39] auto[1] 2 1 T269 1 T222 1 - -
auto[40:43] auto[0] 8 1 T28 2 T73 2 T237 2
auto[40:43] auto[1] 8 1 T28 2 T73 2 T237 2
auto[44:47] auto[0] 13 1 T66 4 T192 2 T217 1
auto[44:47] auto[1] 13 1 T66 4 T192 2 T217 1
auto[48:51] auto[0] 12 1 T63 1 T27 3 T223 1
auto[48:51] auto[1] 12 1 T63 1 T27 3 T223 1
auto[52:55] auto[0] 95 1 T1 1 T8 4 T42 1
auto[52:55] auto[1] 95 1 T1 1 T8 4 T42 1
auto[56:59] auto[0] 92 1 T1 3 T9 1 T10 1
auto[56:59] auto[1] 194 1 T1 3 T9 1 T10 1
auto[60:63] auto[0] 10 1 T1 1 T62 3 T188 1
auto[60:63] auto[1] 10 1 T1 1 T62 3 T188 1
auto[64:67] auto[0] 11 1 T59 5 T343 1 T227 1
auto[64:67] auto[1] 11 1 T59 5 T343 1 T227 1
auto[68:71] auto[0] 5 1 T320 2 T220 1 T283 1
auto[68:71] auto[1] 5 1 T320 2 T220 1 T283 1
auto[72:75] auto[0] 14 1 T76 1 T339 2 T72 3
auto[72:75] auto[1] 14 1 T76 1 T339 2 T72 3
auto[76:79] auto[0] 6 1 T8 1 T61 1 T206 1
auto[76:79] auto[1] 6 1 T8 1 T61 1 T206 1
auto[80:83] auto[0] 7 1 T198 2 T64 3 T320 2
auto[80:83] auto[1] 7 1 T198 2 T64 3 T320 2
auto[84:87] auto[0] 10 1 T8 3 T65 1 T200 1
auto[84:87] auto[1] 10 1 T8 3 T65 1 T200 1
auto[88:91] auto[0] 90 1 T9 1 T62 1 T42 1
auto[88:91] auto[1] 90 1 T9 1 T62 1 T42 1
auto[92:95] auto[0] 13 1 T61 3 T27 1 T28 1
auto[92:95] auto[1] 13 1 T61 3 T27 1 T28 1
auto[96:99] auto[0] 14 1 T42 2 T68 3 T206 3
auto[96:99] auto[1] 14 1 T42 2 T68 3 T206 3
auto[100:103] auto[0] 15 1 T11 1 T67 5 T227 1
auto[100:103] auto[1] 15 1 T11 1 T67 5 T227 1
auto[104:107] auto[0] 91 1 T1 1 T9 1 T10 3
auto[104:107] auto[1] 198 1 T1 1 T9 1 T10 3
auto[108:111] auto[0] 13 1 T1 1 T61 2 T67 1
auto[108:111] auto[1] 13 1 T1 1 T61 2 T67 1
auto[112:115] auto[0] 8 1 T191 1 T223 2 T341 2
auto[112:115] auto[1] 8 1 T191 1 T223 2 T341 2
auto[116:119] auto[0] 4 1 T66 2 T70 1 T287 1
auto[116:119] auto[1] 4 1 T66 2 T70 1 T287 1
auto[120:123] auto[0] 12 1 T188 4 T43 1 T78 1
auto[120:123] auto[1] 12 1 T188 4 T43 1 T78 1
auto[124:127] auto[0] 15 1 T8 1 T88 1 T200 1
auto[124:127] auto[1] 15 1 T8 1 T88 1 T200 1
auto[128:131] auto[0] 13 1 T88 1 T194 1 T198 1
auto[128:131] auto[1] 13 1 T88 1 T194 1 T198 1
auto[132:135] auto[0] 12 1 T60 1 T190 3 T67 1
auto[132:135] auto[1] 12 1 T60 1 T190 3 T67 1
auto[136:139] auto[0] 13 1 T11 1 T191 2 T223 1
auto[136:139] auto[1] 13 1 T11 1 T191 2 T223 1
auto[140:143] auto[0] 7 1 T1 1 T326 2 T198 1
auto[140:143] auto[1] 7 1 T1 1 T326 2 T198 1
auto[144:147] auto[0] 9 1 T10 2 T278 2 T375 2
auto[144:147] auto[1] 9 1 T10 2 T278 2 T375 2
auto[148:151] auto[0] 15 1 T28 2 T227 2 T218 3
auto[148:151] auto[1] 15 1 T28 2 T227 2 T218 3
auto[152:155] auto[0] 8 1 T275 1 T248 1 T74 2
auto[152:155] auto[1] 8 1 T275 1 T248 1 T74 2
auto[156:159] auto[0] 80 1 T1 1 T62 1 T42 3
auto[156:159] auto[1] 80 1 T1 1 T62 1 T42 3
auto[160:163] auto[0] 7 1 T78 1 T185 1 T198 1
auto[160:163] auto[1] 7 1 T78 1 T185 1 T198 1
auto[164:167] auto[0] 12 1 T8 2 T69 1 T203 1
auto[164:167] auto[1] 12 1 T8 2 T69 1 T203 1
auto[168:171] auto[0] 17 1 T65 1 T88 2 T68 3
auto[168:171] auto[1] 17 1 T65 1 T88 2 T68 3
auto[172:175] auto[0] 13 1 T88 2 T69 2 T217 2
auto[172:175] auto[1] 13 1 T88 2 T69 2 T217 2
auto[176:179] auto[0] 6 1 T67 1 T279 1 T202 2
auto[176:179] auto[1] 6 1 T67 1 T279 1 T202 2
auto[180:183] auto[0] 31 1 T26 1 T27 1 T28 2
auto[180:183] auto[1] 31 1 T26 1 T27 1 T28 2
auto[184:187] auto[0] 98 1 T62 2 T47 1 T61 1
auto[184:187] auto[1] 205 1 T62 2 T47 1 T61 1
auto[188:191] auto[0] 7 1 T341 1 T228 2 T202 1
auto[188:191] auto[1] 7 1 T341 1 T228 2 T202 1
auto[192:195] auto[0] 10 1 T8 2 T12 1 T191 1
auto[192:195] auto[1] 10 1 T8 2 T12 1 T191 1
auto[196:199] auto[0] 3 1 T10 1 T249 1 T283 1
auto[196:199] auto[1] 3 1 T10 1 T249 1 T283 1
auto[200:203] auto[0] 12 1 T11 1 T63 1 T193 1
auto[200:203] auto[1] 12 1 T11 1 T63 1 T193 1
auto[204:207] auto[0] 11 1 T66 1 T68 1 T79 1
auto[204:207] auto[1] 11 1 T66 1 T68 1 T79 1
auto[208:211] auto[0] 4 1 T255 1 T250 1 T226 1
auto[208:211] auto[1] 4 1 T255 1 T250 1 T226 1
auto[212:215] auto[0] 9 1 T341 1 T324 5 T214 1
auto[212:215] auto[1] 9 1 T341 1 T324 5 T214 1
auto[216:219] auto[0] 13 1 T10 2 T62 2 T59 2
auto[216:219] auto[1] 13 1 T10 2 T62 2 T59 2
auto[220:223] auto[0] 9 1 T59 3 T77 1 T69 1
auto[220:223] auto[1] 9 1 T59 3 T77 1 T69 1
auto[224:227] auto[0] 11 1 T61 1 T188 1 T275 1
auto[224:227] auto[1] 11 1 T61 1 T188 1 T275 1
auto[228:231] auto[0] 7 1 T67 3 T268 1 T376 1
auto[228:231] auto[1] 7 1 T67 3 T268 1 T376 1
auto[232:235] auto[0] 128 1 T1 2 T8 1 T9 1
auto[232:235] auto[1] 251 1 T1 2 T8 1 T9 1
auto[236:239] auto[0] 12 1 T59 1 T65 1 T27 1
auto[236:239] auto[1] 12 1 T59 1 T65 1 T27 1
auto[240:243] auto[0] 7 1 T279 3 T195 1 T317 2
auto[240:243] auto[1] 7 1 T279 3 T195 1 T317 2
auto[244:247] auto[0] 5 1 T194 1 T320 2 T240 1
auto[244:247] auto[1] 5 1 T194 1 T320 2 T240 1
auto[248:251] auto[0] 11 1 T43 2 T28 1 T279 1
auto[248:251] auto[1] 11 1 T43 2 T28 1 T279 1
auto[252:255] auto[0] 10 1 T68 2 T339 1 T259 2
auto[252:255] auto[1] 10 1 T68 2 T339 1 T259 2

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