Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.52	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	4	56	93.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	4	56	93.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	92	1			T47	2		T89	2		T137	4
auto[ReadAddrCrossIntoMailbox]	30	1			T47	2		T90	8		T229	4
auto[ReadAddrCrossOutOfMailbox]	34	1			T90	6		T254	2		T229	4
auto[ReadAddrCrossAllMailbox]	36	1			T90	4		T137	2		T225	2
auto[ReadAddrOutsideMailbox]	830	1			T1	12		T8	4		T9	16

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511

1

T1

6

T8

2

T9

8

auto[1]

511

1

T1

6

T8

2

T9

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	182	1			T8	2		T9	8		T76	2
read_ops[0x0b]	124	1			T1	2		T9	2		T62	2
read_ops[0x3b]	178	1			T1	6		T9	2		T10	2
read_ops[0x6b]	174	1			T1	2		T9	2		T11	2
read_ops[0xbb]	172	1			T62	2		T47	2		T61	2
read_ops[0xeb]	192	1			T1	2		T8	2		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2
[read_ops[0x0b]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	3	1			T239	1		T229	1		T331	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	3	1			T239	1		T229	1		T331	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T229	1		T332	2		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T229	1		T332	2		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T233	1		T267	1		T353	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T233	1		T267	1		T353	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T267	1		T310	1		T331	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T267	1		T310	1		T331	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	79	1			T8	1		T9	4		T76	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	79	1			T8	1		T9	4		T76	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T252	1		T45	2		T231	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T252	1		T45	2		T231	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T229	1		T327	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T229	1		T327	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	51	1			T1	1		T9	1		T62	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	51	1			T1	1		T9	1		T62	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T137	1		T252	2		T45	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T137	1		T252	2		T45	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T238	1		T233	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T238	1		T233	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T238	1		T327	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T238	1		T327	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T137	1		T327	2		T332	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T137	1		T327	2		T332	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	70	1			T1	3		T9	1		T10	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T1	3		T9	1		T10	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T137	1		T252	2		T45	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T137	1		T252	2		T45	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T90	2		T229	1		T270	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T90	2		T229	1		T270	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T225	1		T238	3		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T225	1		T238	3		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T225	1		T238	1		T233	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T225	1		T238	1		T233	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T1	1		T9	1		T11	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	68	1			T1	1		T9	1		T11	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T89	1		T252	1		T212	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T89	1		T252	1		T212	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T47	1		T90	1		T327	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T47	1		T90	1		T327	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T90	2		T330	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T90	2		T330	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T90	2		T212	1		T233	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T90	2		T212	1		T233	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	67	1			T62	1		T61	1		T190	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	67	1			T62	1		T61	1		T190	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T47	1		T254	1		T229	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T47	1		T254	1		T229	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T90	1		T310	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T90	1		T310	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T90	1		T254	1		T229	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T90	1		T254	1		T229	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T330	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T330	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	80	1			T1	1		T8	1		T9	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	80	1			T1	1		T8	1		T9	1