Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	303425	1			T1	1668		T2	1164		T3	1
all_pins[1]	303425	1			T1	1668		T2	1164		T3	1
all_pins[2]	303425	1			T1	1668		T2	1164		T3	1
all_pins[3]	303425	1			T1	1668		T2	1164		T3	1
all_pins[4]	303425	1			T1	1668		T2	1164		T3	1
all_pins[5]	303425	1			T1	1668		T2	1164		T3	1
all_pins[6]	303425	1			T1	1668		T2	1164		T3	1
all_pins[7]	303425	1			T1	1668		T2	1164		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2426589	1			T1	13344		T2	9312		T3	8
values[0x1]	811	1			T21	36		T38	33		T39	12
transitions[0x0=>0x1]	629	1			T21	27		T38	22		T39	12
transitions[0x1=>0x0]	638	1			T21	28		T38	22		T39	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	303317	1			T1	1668		T2	1164		T3	1
all_pins[0]	values[0x1]	108	1			T21	2		T38	2		T39	4
all_pins[0]	transitions[0x0=>0x1]	80	1			T21	1		T39	4		T40	3
all_pins[0]	transitions[0x1=>0x0]	73	1			T21	5		T38	6		T39	1
all_pins[1]	values[0x0]	303324	1			T1	1668		T2	1164		T3	1
all_pins[1]	values[0x1]	101	1			T21	6		T38	8		T39	1
all_pins[1]	transitions[0x0=>0x1]	82	1			T21	3		T38	2		T39	1
all_pins[1]	transitions[0x1=>0x0]	75	1			T21	4		T39	1		T40	5
all_pins[2]	values[0x0]	303331	1			T1	1668		T2	1164		T3	1
all_pins[2]	values[0x1]	94	1			T21	7		T38	6		T39	1
all_pins[2]	transitions[0x0=>0x1]	74	1			T21	7		T38	4		T39	1
all_pins[2]	transitions[0x1=>0x0]	78	1			T21	4		T38	2		T39	2
all_pins[3]	values[0x0]	303327	1			T1	1668		T2	1164		T3	1
all_pins[3]	values[0x1]	98	1			T21	4		T38	4		T39	2
all_pins[3]	transitions[0x0=>0x1]	76	1			T21	3		T38	4		T39	2
all_pins[3]	transitions[0x1=>0x0]	74	1			T21	1		T38	4		T39	1
all_pins[4]	values[0x0]	303329	1			T1	1668		T2	1164		T3	1
all_pins[4]	values[0x1]	96	1			T21	2		T38	4		T39	1
all_pins[4]	transitions[0x0=>0x1]	75	1			T21	1		T38	3		T39	1
all_pins[4]	transitions[0x1=>0x0]	86	1			T21	5		T38	2		T39	1
all_pins[5]	values[0x0]	303318	1			T1	1668		T2	1164		T3	1
all_pins[5]	values[0x1]	107	1			T21	6		T38	3		T39	1
all_pins[5]	transitions[0x0=>0x1]	77	1			T21	4		T38	3		T39	1
all_pins[5]	transitions[0x1=>0x0]	82	1			T21	1		T38	4		T39	2
all_pins[6]	values[0x0]	303313	1			T1	1668		T2	1164		T3	1
all_pins[6]	values[0x1]	112	1			T21	3		T38	4		T39	2
all_pins[6]	transitions[0x0=>0x1]	93	1			T21	3		T38	4		T39	2
all_pins[6]	transitions[0x1=>0x0]	76	1			T21	6		T38	2		T40	9
all_pins[7]	values[0x0]	303330	1			T1	1668		T2	1164		T3	1
all_pins[7]	values[0x1]	95	1			T21	6		T38	2		T40	12
all_pins[7]	transitions[0x0=>0x1]	72	1			T21	5		T38	2		T40	11
all_pins[7]	transitions[0x1=>0x0]	94	1			T21	2		T38	2		T39	4