Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.96	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	57	71	55.47

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	57	71	55.47	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	622	1			T6	2		T10	28		T11	10
values[1]	524	1			T47	4		T66	22		T67	26
values[2]	452	1			T12	2		T88	32		T90	20
values[3]	340	1			T185	34		T186	6		T187	6
values[4]	222	1			T59	24		T42	28		T89	2
values[5]	384	1			T9	18		T62	26		T77	4
values[6]	276	1			T1	26		T8	30		T188	12
values[7]	368	1			T27	18		T24	2		T189	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	446	1			T11	10		T42	28		T60	12
values[1]	550	1			T8	30		T9	18		T12	2
values[2]	412	1			T59	24		T88	32		T27	18
values[3]	246	1			T77	4		T26	4		T91	14
values[4]	370	1			T76	14		T190	20		T24	2
values[5]	220	1			T62	26		T45	12		T184	2
values[6]	422	1			T10	28		T86	4		T78	12
values[7]	522	1			T1	26		T6	2		T47	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3136

1

T1

26

T6

2

T8

30

auto[1]

52

1

T59

12

T60

2

T61

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	57	71	55.47	57

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[3]]	0	1	1
[auto[0]]	[values[4]]	[values[7]]	0	1	1
[auto[0]]	[values[6]]	[values[4]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	6
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[1]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[2]]	[values[5]]	0	1	1
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	7
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[7]]	[values[5] , values[6] , values[7]]	--	--	3

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	136	1			T11	10		T60	10		T87	4
auto[0]	values[0]	values[1]	176	1			T63	16		T191	16		T192	12
auto[0]	values[0]	values[2]	64	1			T193	24		T194	8		T106	16
auto[0]	values[0]	values[4]	72	1			T76	14		T190	20		T195	16
auto[0]	values[0]	values[5]	16	1			T196	12		T197	4		-	-
auto[0]	values[0]	values[6]	102	1			T10	28		T28	34		T198	16
auto[0]	values[0]	values[7]	44	1			T6	2		T68	20		T199	14
auto[0]	values[1]	values[0]	24	1			T137	6		T200	12		T201	6
auto[0]	values[1]	values[1]	56	1			T66	22		T202	34		-	-
auto[0]	values[1]	values[2]	66	1			T203	20		T204	4		T205	2
auto[0]	values[1]	values[3]	30	1			T206	28		T207	2		-	-
auto[0]	values[1]	values[4]	78	1			T183	12		T72	16		T208	14
auto[0]	values[1]	values[5]	14	1			T113	12		T209	2		-	-
auto[0]	values[1]	values[6]	56	1			T78	12		T210	10		T211	14
auto[0]	values[1]	values[7]	196	1			T47	4		T67	26		T79	16
auto[0]	values[2]	values[0]	52	1			T90	20		T212	24		T213	8
auto[0]	values[2]	values[1]	30	1			T12	2		T214	28		-	-
auto[0]	values[2]	values[2]	66	1			T88	32		T215	6		T216	28
auto[0]	values[2]	values[3]	72	1			T217	36		T218	14		T219	8
auto[0]	values[2]	values[4]	66	1			T73	26		T46	6		T220	6
auto[0]	values[2]	values[5]	36	1			T221	12		T222	24		-	-
auto[0]	values[2]	values[6]	64	1			T44	18		T223	16		T224	2
auto[0]	values[2]	values[7]	58	1			T225	10		T226	22		T107	16
auto[0]	values[3]	values[0]	112	1			T185	34		T186	6		T227	16
auto[0]	values[3]	values[1]	50	1			T71	22		T228	28		-	-
auto[0]	values[3]	values[2]	32	1			T229	14		T230	18		-	-
auto[0]	values[3]	values[3]	46	1			T231	8		T232	22		T233	10
auto[0]	values[3]	values[4]	26	1			T234	4		T235	22		-	-
auto[0]	values[3]	values[5]	30	1			T236	30		-	-		-	-
auto[0]	values[3]	values[6]	34	1			T237	22		T238	12		-	-
auto[0]	values[3]	values[7]	8	1			T187	6		T239	2		-	-
auto[0]	values[4]	values[0]	60	1			T42	28		T89	2		T25	14
auto[0]	values[4]	values[1]	10	1			T240	10		-	-		-	-
auto[0]	values[4]	values[2]	42	1			T59	12		T241	4		T242	2
auto[0]	values[4]	values[3]	14	1			T243	2		T244	6		T174	6
auto[0]	values[4]	values[4]	20	1			T245	16		T246	2		T247	2
auto[0]	values[4]	values[5]	28	1			T45	12		T248	16		-	-
auto[0]	values[4]	values[6]	36	1			T249	10		T250	24		T251	2
auto[0]	values[5]	values[0]	26	1			T252	16		T253	10		-	-
auto[0]	values[5]	values[1]	64	1			T9	18		T61	26		T254	6
auto[0]	values[5]	values[2]	58	1			T255	10		T256	8		T257	32
auto[0]	values[5]	values[3]	54	1			T77	4		T26	4		T91	14
auto[0]	values[5]	values[4]	84	1			T109	8		T258	12		T259	26
auto[0]	values[5]	values[5]	42	1			T62	26		T184	2		T182	10
auto[0]	values[5]	values[6]	20	1			T86	4		T260	16		-	-
auto[0]	values[5]	values[7]	28	1			T65	10		T261	6		T262	12
auto[0]	values[6]	values[0]	2	1			T263	2		-	-		-	-
auto[0]	values[6]	values[1]	84	1			T8	30		T188	12		T264	2
auto[0]	values[6]	values[2]	22	1			T265	22		-	-		-	-
auto[0]	values[6]	values[3]	22	1			T266	6		T267	16		-	-
auto[0]	values[6]	values[5]	26	1			T268	6		T269	10		T270	8
auto[0]	values[6]	values[6]	24	1			T271	2		T272	4		T273	18
auto[0]	values[6]	values[7]	94	1			T1	26		T43	10		T274	26
auto[0]	values[7]	values[0]	28	1			T275	14		T276	14		-	-
auto[0]	values[7]	values[1]	70	1			T64	28		T277	16		T278	26
auto[0]	values[7]	values[2]	50	1			T27	18		T279	28		T280	4
auto[0]	values[7]	values[3]	8	1			T281	8		-	-		-	-
auto[0]	values[7]	values[4]	12	1			T24	2		T70	4		T282	2
auto[0]	values[7]	values[5]	28	1			T283	20		T284	8		-	-
auto[0]	values[7]	values[6]	82	1			T189	8		T285	14		T286	30
auto[0]	values[7]	values[7]	86	1			T287	4		T288	6		T289	24
auto[1]	values[0]	values[0]	6	1			T60	2		T69	4		-	-
auto[1]	values[0]	values[7]	6	1			T68	6		-	-		-	-
auto[1]	values[1]	values[4]	4	1			T72	4		-	-		-	-
auto[1]	values[2]	values[4]	4	1			T73	4		-	-		-	-
auto[1]	values[2]	values[6]	4	1			T176	4		-	-		-	-
auto[1]	values[3]	values[1]	2	1			T71	2		-	-		-	-
auto[1]	values[4]	values[2]	12	1			T59	12		-	-		-	-
auto[1]	values[5]	values[1]	8	1			T61	6		T290	2		-	-
auto[1]	values[6]	values[7]	2	1			T74	2		-	-		-	-
auto[1]	values[7]	values[4]	4	1			T70	4		-	-		-	-