Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1418

1

T2

2

T3

5

T14

10

auto[1]

1446

1

T3

11

T14

9

T19

28

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810

1

T2

2

T18

4

T20

4

auto[1]

2054

1

T3

16

T14

19

T19

49

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2553

1

T3

16

T14

19

T19

49

auto[1]

311

1

T2

2

T18

2

T20

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	580	1			T3	3		T14	3		T19	6
valid[1]	581	1			T3	3		T14	3		T19	15
valid[2]	567	1			T3	4		T14	4		T19	13
valid[3]	566	1			T2	1		T3	1		T14	3
valid[4]	570	1			T2	1		T3	5		T14	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	44	1			T51	1		T56	3		T100	2
auto[0]	auto[0]	valid[0]	auto[1]	204	1			T3	1		T14	3		T19	2
auto[0]	auto[0]	valid[1]	auto[0]	53	1			T51	3		T98	2		T99	1
auto[0]	auto[0]	valid[1]	auto[1]	202	1			T14	2		T19	7		T52	4
auto[0]	auto[0]	valid[2]	auto[0]	48	1			T51	2		T402	1		T97	1
auto[0]	auto[0]	valid[2]	auto[1]	203	1			T3	1		T14	3		T19	4
auto[0]	auto[0]	valid[3]	auto[0]	46	1			T56	1		T98	1		T100	1
auto[0]	auto[0]	valid[3]	auto[1]	196	1			T14	1		T19	6		T18	1
auto[0]	auto[0]	valid[4]	auto[0]	53	1			T51	1		T56	1		T98	3
auto[0]	auto[0]	valid[4]	auto[1]	201	1			T3	3		T14	1		T19	2
auto[0]	auto[1]	valid[0]	auto[0]	52	1			T51	2		T56	1		T98	2
auto[0]	auto[1]	valid[0]	auto[1]	225	1			T3	2		T19	4		T20	1
auto[0]	auto[1]	valid[1]	auto[0]	57	1			T18	1		T51	3		T56	1
auto[0]	auto[1]	valid[1]	auto[1]	204	1			T3	3		T14	1		T19	8
auto[0]	auto[1]	valid[2]	auto[0]	44	1			T56	1		T98	1		T99	1
auto[0]	auto[1]	valid[2]	auto[1]	202	1			T3	3		T14	1		T19	9
auto[0]	auto[1]	valid[3]	auto[0]	51	1			T18	1		T20	1		T51	1
auto[0]	auto[1]	valid[3]	auto[1]	216	1			T3	1		T14	2		T19	5
auto[0]	auto[1]	valid[4]	auto[0]	51	1			T56	1		T100	2		T388	1
auto[0]	auto[1]	valid[4]	auto[1]	201	1			T3	2		T14	5		T19	2
auto[1]	auto[0]	valid[0]	auto[0]	32	1			T56	2		T98	2		T57	1
auto[1]	auto[0]	valid[1]	auto[0]	33	1			T18	1		T20	1		T100	1
auto[1]	auto[0]	valid[2]	auto[0]	38	1			T98	2		T57	1		T100	1
auto[1]	auto[0]	valid[3]	auto[0]	32	1			T2	1		T51	2		T54	2
auto[1]	auto[0]	valid[4]	auto[0]	33	1			T2	1		T20	1		T99	1
auto[1]	auto[1]	valid[0]	auto[0]	23	1			T51	1		T98	1		T100	1
auto[1]	auto[1]	valid[1]	auto[0]	32	1			T18	1		T20	1		T51	1
auto[1]	auto[1]	valid[2]	auto[0]	32	1			T99	3		T100	2		T388	1
auto[1]	auto[1]	valid[3]	auto[0]	25	1			T98	1		T99	1		T100	1
auto[1]	auto[1]	valid[4]	auto[0]	31	1			T100	2		T96	2		T97	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal