Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19987

1

T2

20

T13

17

T18

199

auto[1]

20025

1

T3

163

T14

19

T19

601

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32775

1

T2

10

T3

163

T13

10

auto[1]

7237

1

T2

10

T13

7

T18

80

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20729	1			T2	13		T3	80		T13	10
others[1]	3319	1			T3	14		T19	52		T18	20
others[2]	3347	1			T2	4		T3	15		T13	1
others[3]	3817	1			T3	20		T13	2		T19	44
interest[1]	2163	1			T3	9		T13	2		T19	36
interest[4]	13706	1			T2	7		T3	53		T13	9
interest[64]	6637	1			T2	3		T3	25		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	6481	1			T2	6		T13	5		T18	59
auto[0]	auto[0]	others[1]	1049	1			T18	12		T20	4		T22	1
auto[0]	auto[0]	others[2]	1060	1			T2	2		T13	1		T18	8
auto[0]	auto[0]	others[3]	1263	1			T13	1		T18	12		T20	8
auto[0]	auto[0]	interest[1]	727	1			T13	1		T18	11		T20	9
auto[0]	auto[0]	interest[4]	4162	1			T2	3		T13	4		T18	39
auto[0]	auto[0]	interest[64]	2170	1			T2	2		T13	2		T18	17
auto[0]	auto[1]	others[0]	10587	1			T3	80		T14	19		T19	328
auto[0]	auto[1]	others[1]	1668	1			T3	14		T19	52		T18	3
auto[0]	auto[1]	others[2]	1660	1			T3	15		T19	46		T18	4
auto[0]	auto[1]	others[3]	1837	1			T3	20		T19	44		T18	4
auto[0]	auto[1]	interest[1]	1052	1			T3	9		T19	36		T18	3
auto[0]	auto[1]	interest[4]	7171	1			T3	53		T14	19		T19	219
auto[0]	auto[1]	interest[64]	3221	1			T3	25		T19	95		T18	7
auto[1]	auto[0]	others[0]	3661	1			T2	7		T13	5		T18	45
auto[1]	auto[0]	others[1]	602	1			T18	5		T20	6		T51	8
auto[1]	auto[0]	others[2]	627	1			T2	2		T18	6		T20	12
auto[1]	auto[0]	others[3]	717	1			T13	1		T18	13		T20	5
auto[1]	auto[0]	interest[1]	384	1			T13	1		T18	3		T20	2
auto[1]	auto[0]	interest[4]	2373	1			T2	4		T13	5		T18	27
auto[1]	auto[0]	interest[64]	1246	1			T2	1		T18	8		T20	18

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal