Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	477	1			T21	20		T38	14		T39	7
all_values[1]	477	1			T21	20		T38	14		T39	7
all_values[2]	477	1			T21	20		T38	14		T39	7
all_values[3]	477	1			T21	20		T38	14		T39	7
all_values[4]	477	1			T21	20		T38	14		T39	7
all_values[5]	477	1			T21	20		T38	14		T39	7
all_values[6]	477	1			T21	20		T38	14		T39	7
all_values[7]	477	1			T21	20		T38	14		T39	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2091

1

T21

94

T38

47

T39

34

auto[1]

1725

1

T21

66

T38

65

T39

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1546

1

T21

61

T38

39

T39

22

auto[1]

2270

1

T21

99

T38

73

T39

34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2162

1

T21

83

T38

58

T39

30

auto[1]

1654

1

T21

77

T38

54

T39

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	83	1			T21	3		T38	1		T40	8
all_values[0]	auto[0]	auto[0]	auto[1]	51	1			T21	3		T38	1		T39	1
all_values[0]	auto[0]	auto[1]	auto[0]	89	1			T21	5		T38	5		T39	1
all_values[0]	auto[0]	auto[1]	auto[1]	41	1			T39	1		T354	1		T355	2
all_values[0]	auto[1]	auto[0]	auto[1]	124	1			T21	8		T38	4		T39	1
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T21	1		T38	3		T39	3
all_values[1]	auto[0]	auto[0]	auto[0]	90	1			T21	4		T38	1		T39	3
all_values[1]	auto[0]	auto[0]	auto[1]	46	1			T21	3		T40	2		T354	3
all_values[1]	auto[0]	auto[1]	auto[0]	94	1			T21	1		T38	2		T39	1
all_values[1]	auto[0]	auto[1]	auto[1]	40	1			T21	1		T38	5		T40	2
all_values[1]	auto[1]	auto[0]	auto[1]	117	1			T21	6		T38	2		T39	2
all_values[1]	auto[1]	auto[1]	auto[1]	90	1			T21	5		T38	4		T39	1
all_values[2]	auto[0]	auto[0]	auto[0]	117	1			T21	3		T38	3		T39	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T21	3		T38	3		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	73	1			T21	1		T38	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[1]	37	1			T21	2		T38	2		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	107	1			T21	8		T38	2		T39	2
all_values[2]	auto[1]	auto[1]	auto[1]	93	1			T21	3		T38	3		T39	1
all_values[3]	auto[0]	auto[0]	auto[0]	95	1			T21	5		T38	2		T39	1
all_values[3]	auto[0]	auto[0]	auto[1]	43	1			T39	1		T40	2		T169	1
all_values[3]	auto[0]	auto[1]	auto[0]	73	1			T21	3		T38	3		T39	1
all_values[3]	auto[0]	auto[1]	auto[1]	37	1			T21	3		T38	1		T40	3
all_values[3]	auto[1]	auto[0]	auto[1]	137	1			T21	2		T38	2		T39	1
all_values[3]	auto[1]	auto[1]	auto[1]	92	1			T21	7		T38	6		T39	3
all_values[4]	auto[0]	auto[0]	auto[0]	105	1			T21	7		T38	1		T39	3
all_values[4]	auto[0]	auto[0]	auto[1]	46	1			T21	1		T40	1		T354	1
all_values[4]	auto[0]	auto[1]	auto[0]	86	1			T21	5		T38	2		T39	1
all_values[4]	auto[0]	auto[1]	auto[1]	44	1			T38	2		T40	4		T354	2
all_values[4]	auto[1]	auto[0]	auto[1]	114	1			T21	4		T38	5		T39	2
all_values[4]	auto[1]	auto[1]	auto[1]	82	1			T21	3		T38	4		T39	1
all_values[5]	auto[0]	auto[0]	auto[0]	141	1			T21	6		T38	5		T39	2
all_values[5]	auto[0]	auto[1]	auto[0]	129	1			T21	5		T38	4		T39	2
all_values[5]	auto[1]	auto[0]	auto[1]	113	1			T21	3		T38	1		T39	2
all_values[5]	auto[1]	auto[1]	auto[1]	94	1			T21	6		T38	4		T39	1
all_values[6]	auto[0]	auto[0]	auto[0]	97	1			T21	7		T38	3		T40	6
all_values[6]	auto[0]	auto[0]	auto[1]	50	1			T21	3		T39	1		T40	3
all_values[6]	auto[0]	auto[1]	auto[0]	85	1			T21	1		T38	4		T39	2
all_values[6]	auto[0]	auto[1]	auto[1]	46	1			T21	1		T38	2		T356	1
all_values[6]	auto[1]	auto[0]	auto[1]	110	1			T21	7		T38	2		T39	3
all_values[6]	auto[1]	auto[1]	auto[1]	89	1			T21	1		T38	3		T39	1
all_values[7]	auto[0]	auto[0]	auto[0]	92	1			T21	1		T39	3		T354	2
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T21	1		T38	2		T39	2
all_values[7]	auto[0]	auto[1]	auto[0]	97	1			T21	4		T38	2		T40	3
all_values[7]	auto[0]	auto[1]	auto[1]	40	1			T21	1		T38	1		T40	5
all_values[7]	auto[1]	auto[0]	auto[1]	118	1			T21	6		T38	7		T39	2
all_values[7]	auto[1]	auto[1]	auto[1]	85	1			T21	7		T38	2		T40	7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal