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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.04 97.50 92.82 98.61 80.85 95.87 90.94 87.69


Total test records in report: 829
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T371 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4048519214 Apr 23 02:45:13 PM PDT 24 Apr 23 02:45:20 PM PDT 24 550641308 ps
T148 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3807143834 Apr 23 02:45:15 PM PDT 24 Apr 23 02:45:17 PM PDT 24 242007208 ps
T150 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3452328695 Apr 23 02:45:06 PM PDT 24 Apr 23 02:45:09 PM PDT 24 537375178 ps
T758 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.102204046 Apr 23 02:44:35 PM PDT 24 Apr 23 02:44:45 PM PDT 24 1567983450 ps
T759 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2527490015 Apr 23 02:45:27 PM PDT 24 Apr 23 02:45:28 PM PDT 24 16324534 ps
T372 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1325882763 Apr 23 02:45:11 PM PDT 24 Apr 23 02:45:27 PM PDT 24 718469875 ps
T760 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1977417984 Apr 23 02:45:11 PM PDT 24 Apr 23 02:45:12 PM PDT 24 15473502 ps
T761 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3091861 Apr 23 02:44:27 PM PDT 24 Apr 23 02:44:53 PM PDT 24 5037408024 ps
T762 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2797457652 Apr 23 02:45:26 PM PDT 24 Apr 23 02:45:27 PM PDT 24 13141672 ps
T763 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3828462974 Apr 23 02:45:22 PM PDT 24 Apr 23 02:45:23 PM PDT 24 38477696 ps
T764 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3462948927 Apr 23 02:44:59 PM PDT 24 Apr 23 02:45:01 PM PDT 24 48017550 ps
T765 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1857232091 Apr 23 02:44:21 PM PDT 24 Apr 23 02:44:35 PM PDT 24 3212392483 ps
T766 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2823765935 Apr 23 02:45:26 PM PDT 24 Apr 23 02:45:27 PM PDT 24 35316447 ps
T767 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2469525086 Apr 23 02:44:55 PM PDT 24 Apr 23 02:44:58 PM PDT 24 177973625 ps
T768 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3745524148 Apr 23 02:45:22 PM PDT 24 Apr 23 02:45:23 PM PDT 24 20775450 ps
T769 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1436346721 Apr 23 02:44:11 PM PDT 24 Apr 23 02:44:12 PM PDT 24 20326546 ps
T770 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1204061727 Apr 23 02:44:33 PM PDT 24 Apr 23 02:44:36 PM PDT 24 46610670 ps
T771 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4251496727 Apr 23 02:45:09 PM PDT 24 Apr 23 02:45:12 PM PDT 24 141030529 ps
T772 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2024518104 Apr 23 02:45:23 PM PDT 24 Apr 23 02:45:24 PM PDT 24 35721096 ps
T773 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2063357981 Apr 23 02:44:44 PM PDT 24 Apr 23 02:44:47 PM PDT 24 749476184 ps
T774 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1798953030 Apr 23 02:45:03 PM PDT 24 Apr 23 02:45:06 PM PDT 24 159362253 ps
T775 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.694120652 Apr 23 02:45:01 PM PDT 24 Apr 23 02:45:05 PM PDT 24 125718850 ps
T776 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1683783175 Apr 23 02:44:56 PM PDT 24 Apr 23 02:44:58 PM PDT 24 38254373 ps
T777 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2673300024 Apr 23 02:45:00 PM PDT 24 Apr 23 02:45:02 PM PDT 24 51961540 ps
T778 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1144675019 Apr 23 02:45:25 PM PDT 24 Apr 23 02:45:26 PM PDT 24 50307264 ps
T369 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1234144200 Apr 23 02:44:52 PM PDT 24 Apr 23 02:45:05 PM PDT 24 3315848764 ps
T779 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.990806731 Apr 23 02:44:14 PM PDT 24 Apr 23 02:44:34 PM PDT 24 578873213 ps
T780 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2985958059 Apr 23 02:44:58 PM PDT 24 Apr 23 02:45:00 PM PDT 24 27217011 ps
T781 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.135884048 Apr 23 02:44:47 PM PDT 24 Apr 23 02:45:08 PM PDT 24 9132273886 ps
T151 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1764122094 Apr 23 02:44:47 PM PDT 24 Apr 23 02:44:50 PM PDT 24 103790411 ps
T782 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1497030733 Apr 23 02:45:12 PM PDT 24 Apr 23 02:45:14 PM PDT 24 44116939 ps
T783 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.751814242 Apr 23 02:45:01 PM PDT 24 Apr 23 02:45:17 PM PDT 24 647348261 ps
T784 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2991737808 Apr 23 02:44:21 PM PDT 24 Apr 23 02:44:25 PM PDT 24 199146167 ps
T785 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3205946513 Apr 23 02:45:20 PM PDT 24 Apr 23 02:45:21 PM PDT 24 43295817 ps
T152 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1460089336 Apr 23 02:45:04 PM PDT 24 Apr 23 02:45:07 PM PDT 24 663080041 ps
T786 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1185174324 Apr 23 02:44:51 PM PDT 24 Apr 23 02:44:53 PM PDT 24 86036156 ps
T787 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2236028525 Apr 23 02:44:27 PM PDT 24 Apr 23 02:44:32 PM PDT 24 792509054 ps
T788 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.469674138 Apr 23 02:45:09 PM PDT 24 Apr 23 02:45:13 PM PDT 24 55317091 ps
T789 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2926792024 Apr 23 02:44:57 PM PDT 24 Apr 23 02:45:00 PM PDT 24 152870018 ps
T790 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2799246947 Apr 23 02:44:58 PM PDT 24 Apr 23 02:45:00 PM PDT 24 61588027 ps
T791 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1754111528 Apr 23 02:44:31 PM PDT 24 Apr 23 02:44:32 PM PDT 24 47527955 ps
T792 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.956751034 Apr 23 02:44:56 PM PDT 24 Apr 23 02:45:00 PM PDT 24 197271728 ps
T793 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2733797618 Apr 23 02:44:46 PM PDT 24 Apr 23 02:44:47 PM PDT 24 57501267 ps
T794 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2111214923 Apr 23 02:44:54 PM PDT 24 Apr 23 02:44:58 PM PDT 24 135985025 ps
T795 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3478980457 Apr 23 02:44:16 PM PDT 24 Apr 23 02:44:29 PM PDT 24 1976456939 ps
T796 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2204861049 Apr 23 02:45:18 PM PDT 24 Apr 23 02:45:19 PM PDT 24 32737162 ps
T797 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1167680750 Apr 23 02:45:20 PM PDT 24 Apr 23 02:45:21 PM PDT 24 25058493 ps
T798 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1617579705 Apr 23 02:44:21 PM PDT 24 Apr 23 02:44:22 PM PDT 24 179277615 ps
T799 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3418360982 Apr 23 02:45:18 PM PDT 24 Apr 23 02:45:20 PM PDT 24 60687055 ps
T800 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3473149550 Apr 23 02:45:10 PM PDT 24 Apr 23 02:45:14 PM PDT 24 228961705 ps
T801 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4049878817 Apr 23 02:44:24 PM PDT 24 Apr 23 02:44:25 PM PDT 24 14771049 ps
T802 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.963105415 Apr 23 02:44:40 PM PDT 24 Apr 23 02:44:49 PM PDT 24 1528898150 ps
T803 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.162659432 Apr 23 02:45:06 PM PDT 24 Apr 23 02:45:11 PM PDT 24 162522875 ps
T804 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2555464345 Apr 23 02:44:15 PM PDT 24 Apr 23 02:44:20 PM PDT 24 621505772 ps
T805 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.659804643 Apr 23 02:44:46 PM PDT 24 Apr 23 02:44:49 PM PDT 24 527990749 ps
T806 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.94410180 Apr 23 02:45:00 PM PDT 24 Apr 23 02:45:04 PM PDT 24 192169184 ps
T807 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.261348757 Apr 23 02:45:22 PM PDT 24 Apr 23 02:45:23 PM PDT 24 17240685 ps
T808 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.22219650 Apr 23 02:44:13 PM PDT 24 Apr 23 02:44:15 PM PDT 24 105293370 ps
T809 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2997629156 Apr 23 02:45:20 PM PDT 24 Apr 23 02:45:21 PM PDT 24 19885020 ps
T810 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3431928572 Apr 23 02:45:04 PM PDT 24 Apr 23 02:45:05 PM PDT 24 19982383 ps
T811 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1602507321 Apr 23 02:44:29 PM PDT 24 Apr 23 02:44:31 PM PDT 24 122558521 ps
T812 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3398555474 Apr 23 02:44:49 PM PDT 24 Apr 23 02:44:51 PM PDT 24 54231253 ps
T813 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3256120152 Apr 23 02:45:20 PM PDT 24 Apr 23 02:45:21 PM PDT 24 60989560 ps
T814 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1877346909 Apr 23 02:44:23 PM PDT 24 Apr 23 02:44:32 PM PDT 24 605692246 ps
T815 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1942836095 Apr 23 02:45:22 PM PDT 24 Apr 23 02:45:23 PM PDT 24 14019732 ps
T816 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.582371602 Apr 23 02:45:16 PM PDT 24 Apr 23 02:45:19 PM PDT 24 185577725 ps
T817 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2486952555 Apr 23 02:44:58 PM PDT 24 Apr 23 02:45:05 PM PDT 24 418936351 ps
T818 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2048617201 Apr 23 02:44:11 PM PDT 24 Apr 23 02:44:12 PM PDT 24 55975344 ps
T819 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.505235225 Apr 23 02:44:40 PM PDT 24 Apr 23 02:44:43 PM PDT 24 29678671 ps
T820 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2335846375 Apr 23 02:45:13 PM PDT 24 Apr 23 02:45:17 PM PDT 24 115552661 ps
T821 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3111424184 Apr 23 02:44:55 PM PDT 24 Apr 23 02:44:56 PM PDT 24 16233652 ps
T822 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3164451592 Apr 23 02:45:03 PM PDT 24 Apr 23 02:45:26 PM PDT 24 798935493 ps
T823 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1543278583 Apr 23 02:44:34 PM PDT 24 Apr 23 02:44:38 PM PDT 24 296238989 ps
T824 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2569125322 Apr 23 02:44:24 PM PDT 24 Apr 23 02:44:25 PM PDT 24 189336241 ps
T825 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2673035193 Apr 23 02:45:22 PM PDT 24 Apr 23 02:45:23 PM PDT 24 43559488 ps
T826 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3346422003 Apr 23 02:44:29 PM PDT 24 Apr 23 02:44:31 PM PDT 24 58573834 ps
T827 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2579343182 Apr 23 02:45:10 PM PDT 24 Apr 23 02:45:14 PM PDT 24 189183424 ps
T828 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1859970138 Apr 23 02:44:57 PM PDT 24 Apr 23 02:44:58 PM PDT 24 11283680 ps
T829 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2341767734 Apr 23 02:44:16 PM PDT 24 Apr 23 02:44:18 PM PDT 24 211149878 ps

Test location /workspace/coverage/default/27.spi_device_upload.2283941180
Short name T1
Test name
Test status
Simulation time 11493775421 ps
CPU time 40.54 seconds
Started Apr 23 03:20:39 PM PDT 24
Finished Apr 23 03:21:20 PM PDT 24
Peak memory 233648 kb
Host smart-d0003f1a-9602-4ae3-bdeb-dc54827dc1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283941180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2283941180
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1830246515
Short name T18
Test name
Test status
Simulation time 5003532352 ps
CPU time 26.52 seconds
Started Apr 23 03:24:24 PM PDT 24
Finished Apr 23 03:24:52 PM PDT 24
Peak memory 216824 kb
Host smart-34bb59ad-d173-4723-94e3-ec7531abc27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830246515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1830246515
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.560589950
Short name T34
Test name
Test status
Simulation time 953607644 ps
CPU time 20.21 seconds
Started Apr 23 02:45:09 PM PDT 24
Finished Apr 23 02:45:29 PM PDT 24
Peak memory 215460 kb
Host smart-89f8a9f5-d6fc-4baa-bdff-04aad0898633
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560589950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.560589950
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1055836863
Short name T44
Test name
Test status
Simulation time 1504518982 ps
CPU time 19.21 seconds
Started Apr 23 03:22:17 PM PDT 24
Finished Apr 23 03:22:37 PM PDT 24
Peak memory 250368 kb
Host smart-b60ec1a0-ff65-4407-91be-5b1ef7df1320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055836863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1055836863
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.399300131
Short name T21
Test name
Test status
Simulation time 172306594 ps
CPU time 1.05 seconds
Started Apr 23 03:23:16 PM PDT 24
Finished Apr 23 03:23:17 PM PDT 24
Peak memory 207580 kb
Host smart-07c48a8f-d33c-455e-8bea-ee04ca446314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399300131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.399300131
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3517291308
Short name T9
Test name
Test status
Simulation time 2832941072 ps
CPU time 26.26 seconds
Started Apr 23 03:17:44 PM PDT 24
Finished Apr 23 03:18:11 PM PDT 24
Peak memory 234340 kb
Host smart-511b90cb-0f5b-46ee-97ff-ce344e2f0310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517291308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3517291308
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4028549100
Short name T390
Test name
Test status
Simulation time 7179365492 ps
CPU time 31.12 seconds
Started Apr 23 03:20:07 PM PDT 24
Finished Apr 23 03:20:39 PM PDT 24
Peak memory 221564 kb
Host smart-d7eddd75-8cb9-4ef7-a5cf-c3c22c1710f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028549100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4028549100
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.125881171
Short name T61
Test name
Test status
Simulation time 1452775354 ps
CPU time 9.85 seconds
Started Apr 23 03:18:44 PM PDT 24
Finished Apr 23 03:18:54 PM PDT 24
Peak memory 237200 kb
Host smart-e1a7ecd2-c3d6-4490-8ad8-1c436df1117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125881171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.125881171
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.557191003
Short name T96
Test name
Test status
Simulation time 115609846545 ps
CPU time 55.53 seconds
Started Apr 23 03:23:52 PM PDT 24
Finished Apr 23 03:24:48 PM PDT 24
Peak memory 216972 kb
Host smart-af02efe7-10f9-407b-a81d-712560738512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557191003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.557191003
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.357586416
Short name T6
Test name
Test status
Simulation time 136752069 ps
CPU time 2.42 seconds
Started Apr 23 03:15:07 PM PDT 24
Finished Apr 23 03:15:10 PM PDT 24
Peak memory 223444 kb
Host smart-58645cb9-c1c4-4ee1-8e33-b9bd33c5202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357586416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.357586416
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.398516055
Short name T41
Test name
Test status
Simulation time 30487273 ps
CPU time 0.72 seconds
Started Apr 23 03:14:00 PM PDT 24
Finished Apr 23 03:14:02 PM PDT 24
Peak memory 216624 kb
Host smart-fc9df3b4-a86d-4a13-9df2-762cce5e6079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398516055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.398516055
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/22.spi_device_intercept.300745334
Short name T45
Test name
Test status
Simulation time 4544979514 ps
CPU time 8.74 seconds
Started Apr 23 03:19:36 PM PDT 24
Finished Apr 23 03:19:45 PM PDT 24
Peak memory 221868 kb
Host smart-c00fa27a-88f2-4af2-914b-b5455c560a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300745334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.300745334
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2971661687
Short name T98
Test name
Test status
Simulation time 6722721405 ps
CPU time 47.42 seconds
Started Apr 23 03:16:13 PM PDT 24
Finished Apr 23 03:17:01 PM PDT 24
Peak memory 216956 kb
Host smart-014531b6-16c1-4bd3-bd42-dd92d2d1ffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971661687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2971661687
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1281642796
Short name T81
Test name
Test status
Simulation time 1526404313 ps
CPU time 22.04 seconds
Started Apr 23 03:18:36 PM PDT 24
Finished Apr 23 03:18:58 PM PDT 24
Peak memory 241460 kb
Host smart-ea4cb0b9-e532-476c-ae24-25cc7fe0c198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281642796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1281642796
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3528631566
Short name T48
Test name
Test status
Simulation time 261883556 ps
CPU time 1.12 seconds
Started Apr 23 03:15:01 PM PDT 24
Finished Apr 23 03:15:03 PM PDT 24
Peak memory 235416 kb
Host smart-485a6b02-c08b-455c-a734-50950ee3bead
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528631566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3528631566
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.249717683
Short name T117
Test name
Test status
Simulation time 178812327 ps
CPU time 2.62 seconds
Started Apr 23 02:44:44 PM PDT 24
Finished Apr 23 02:44:47 PM PDT 24
Peak memory 215612 kb
Host smart-344b7df8-77d3-4930-8ec6-17c5e5a7fcf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249717683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.249717683
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.895449109
Short name T90
Test name
Test status
Simulation time 1267333293 ps
CPU time 9.93 seconds
Started Apr 23 03:23:32 PM PDT 24
Finished Apr 23 03:23:42 PM PDT 24
Peak memory 233768 kb
Host smart-a8b3e951-e864-487e-ae2f-639c9c816234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895449109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.895449109
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2961759809
Short name T279
Test name
Test status
Simulation time 300254735 ps
CPU time 6.6 seconds
Started Apr 23 03:16:47 PM PDT 24
Finished Apr 23 03:16:54 PM PDT 24
Peak memory 233196 kb
Host smart-40c60cea-2d39-4ade-92ed-592277d498c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961759809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2961759809
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1381391923
Short name T217
Test name
Test status
Simulation time 2531130873 ps
CPU time 7.61 seconds
Started Apr 23 03:20:08 PM PDT 24
Finished Apr 23 03:20:17 PM PDT 24
Peak memory 219100 kb
Host smart-ef20af75-938f-40f7-ba44-05d396fdb9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381391923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1381391923
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_upload.2549355363
Short name T42
Test name
Test status
Simulation time 30938133130 ps
CPU time 31.47 seconds
Started Apr 23 03:23:31 PM PDT 24
Finished Apr 23 03:24:03 PM PDT 24
Peak memory 216972 kb
Host smart-bf3c8f5d-67a8-4608-a0cf-d4f6765a4147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549355363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2549355363
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3500559730
Short name T283
Test name
Test status
Simulation time 54238218413 ps
CPU time 38.83 seconds
Started Apr 23 03:14:33 PM PDT 24
Finished Apr 23 03:15:12 PM PDT 24
Peak memory 238688 kb
Host smart-dc260e85-2f6e-4eb8-81c8-a7048ae10a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500559730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3500559730
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.832782005
Short name T138
Test name
Test status
Simulation time 38777029 ps
CPU time 2.48 seconds
Started Apr 23 02:44:11 PM PDT 24
Finished Apr 23 02:44:14 PM PDT 24
Peak memory 215192 kb
Host smart-94a512a7-b1e4-4923-bb3f-0526b53d49b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832782005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.832782005
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.553792865
Short name T59
Test name
Test status
Simulation time 4031264463 ps
CPU time 17.58 seconds
Started Apr 23 03:21:13 PM PDT 24
Finished Apr 23 03:21:30 PM PDT 24
Peak memory 231016 kb
Host smart-023d7446-7137-4f9c-aa6c-62edc8b56185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553792865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.553792865
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1280399663
Short name T198
Test name
Test status
Simulation time 9437155262 ps
CPU time 12.25 seconds
Started Apr 23 03:15:19 PM PDT 24
Finished Apr 23 03:15:32 PM PDT 24
Peak memory 234624 kb
Host smart-c62d2134-f4c2-4b22-b1ef-f9fe59e1548e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280399663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1280399663
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.830153123
Short name T19
Test name
Test status
Simulation time 66225432883 ps
CPU time 20.86 seconds
Started Apr 23 03:18:40 PM PDT 24
Finished Apr 23 03:19:01 PM PDT 24
Peak memory 216900 kb
Host smart-a91b9a93-d876-4ccf-882a-bf65c9c547c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830153123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.830153123
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1965945930
Short name T226
Test name
Test status
Simulation time 3503070643 ps
CPU time 11.13 seconds
Started Apr 23 03:19:13 PM PDT 24
Finished Apr 23 03:19:24 PM PDT 24
Peak memory 219660 kb
Host smart-abd526c6-ec24-4196-beee-c31f029b3df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965945930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1965945930
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.924069141
Short name T222
Test name
Test status
Simulation time 158930728426 ps
CPU time 29.44 seconds
Started Apr 23 03:22:18 PM PDT 24
Finished Apr 23 03:22:48 PM PDT 24
Peak memory 233612 kb
Host smart-09b0303e-96a2-4baf-a668-0142996ccc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924069141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.924069141
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.95232931
Short name T229
Test name
Test status
Simulation time 4991118512 ps
CPU time 19.49 seconds
Started Apr 23 03:24:14 PM PDT 24
Finished Apr 23 03:24:35 PM PDT 24
Peak memory 222840 kb
Host smart-971312e2-354f-491d-bb9b-15a710a8af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95232931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.95232931
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1297347364
Short name T67
Test name
Test status
Simulation time 3001632575 ps
CPU time 14.67 seconds
Started Apr 23 03:21:12 PM PDT 24
Finished Apr 23 03:21:27 PM PDT 24
Peak memory 234536 kb
Host smart-c330c220-77f0-487e-ae8a-077d3890a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297347364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1297347364
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2013916702
Short name T378
Test name
Test status
Simulation time 25242694821 ps
CPU time 70.07 seconds
Started Apr 23 03:18:55 PM PDT 24
Finished Apr 23 03:20:06 PM PDT 24
Peak memory 216936 kb
Host smart-57dbf2f5-81f0-46ca-a5c6-8a5b608ae6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013916702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2013916702
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2978827056
Short name T216
Test name
Test status
Simulation time 394418620 ps
CPU time 7.62 seconds
Started Apr 23 03:21:48 PM PDT 24
Finished Apr 23 03:21:57 PM PDT 24
Peak memory 233148 kb
Host smart-d0e98540-c611-46bd-8d6c-b8680a9b128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978827056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2978827056
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.612428984
Short name T106
Test name
Test status
Simulation time 1696544780 ps
CPU time 19 seconds
Started Apr 23 03:24:08 PM PDT 24
Finished Apr 23 03:24:28 PM PDT 24
Peak memory 233196 kb
Host smart-521ce60c-753a-44cb-9f4c-900432707a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612428984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.612428984
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.481965707
Short name T68
Test name
Test status
Simulation time 73948038100 ps
CPU time 52.19 seconds
Started Apr 23 03:22:39 PM PDT 24
Finished Apr 23 03:23:31 PM PDT 24
Peak memory 233212 kb
Host smart-6f0b582b-1afe-493a-b1e6-57a468d35a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481965707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.481965707
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3330853794
Short name T401
Test name
Test status
Simulation time 46367174274 ps
CPU time 47.16 seconds
Started Apr 23 03:16:57 PM PDT 24
Finished Apr 23 03:17:45 PM PDT 24
Peak memory 216936 kb
Host smart-6386e056-2933-4fdf-a8fe-7c054a90dfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330853794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3330853794
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.681359549
Short name T238
Test name
Test status
Simulation time 4622116099 ps
CPU time 13.6 seconds
Started Apr 23 03:23:55 PM PDT 24
Finished Apr 23 03:24:09 PM PDT 24
Peak memory 233220 kb
Host smart-23c24804-8ba7-448a-af6d-73f9477a03b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681359549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.681359549
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_upload.2386258036
Short name T28
Test name
Test status
Simulation time 808117562 ps
CPU time 8.1 seconds
Started Apr 23 03:15:41 PM PDT 24
Finished Apr 23 03:15:50 PM PDT 24
Peak memory 233636 kb
Host smart-3637ad8b-0689-4d7a-a36b-cb334218ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386258036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2386258036
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.961037767
Short name T341
Test name
Test status
Simulation time 1442638615 ps
CPU time 8.91 seconds
Started Apr 23 03:18:46 PM PDT 24
Finished Apr 23 03:18:55 PM PDT 24
Peak memory 237392 kb
Host smart-8bedc82e-0041-4269-8c4b-69ef97a17684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961037767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.961037767
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1934489449
Short name T71
Test name
Test status
Simulation time 57644174194 ps
CPU time 43.2 seconds
Started Apr 23 03:16:13 PM PDT 24
Finished Apr 23 03:16:57 PM PDT 24
Peak memory 238160 kb
Host smart-6fdc449d-08cc-44ca-8cbd-fb82188d8d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934489449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1934489449
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3377830379
Short name T107
Test name
Test status
Simulation time 4666307765 ps
CPU time 42.58 seconds
Started Apr 23 03:23:54 PM PDT 24
Finished Apr 23 03:24:37 PM PDT 24
Peak memory 218952 kb
Host smart-c34b7ebb-fa20-4fa3-892b-00d9cafd98d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377830379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3377830379
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1498435629
Short name T124
Test name
Test status
Simulation time 344389546 ps
CPU time 3.73 seconds
Started Apr 23 02:45:04 PM PDT 24
Finished Apr 23 02:45:08 PM PDT 24
Peak memory 215404 kb
Host smart-3ed0b528-51a7-4f09-aedd-9b1020f0fffb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498435629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1498435629
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/24.spi_device_upload.1299853676
Short name T78
Test name
Test status
Simulation time 13911782153 ps
CPU time 13.38 seconds
Started Apr 23 03:19:59 PM PDT 24
Finished Apr 23 03:20:13 PM PDT 24
Peak memory 216880 kb
Host smart-7523730d-d739-4e8d-a233-30666d40e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299853676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1299853676
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2428882367
Short name T299
Test name
Test status
Simulation time 8874238883 ps
CPU time 32.82 seconds
Started Apr 23 03:16:49 PM PDT 24
Finished Apr 23 03:17:22 PM PDT 24
Peak memory 225112 kb
Host smart-a58a6522-44ad-43d8-9aab-0f56bd84e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428882367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2428882367
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.646890536
Short name T195
Test name
Test status
Simulation time 1954962785 ps
CPU time 7.86 seconds
Started Apr 23 03:19:27 PM PDT 24
Finished Apr 23 03:19:36 PM PDT 24
Peak memory 238756 kb
Host smart-5167c5ea-e0b0-475b-9256-66ef9dd878df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646890536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.646890536
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3125046898
Short name T395
Test name
Test status
Simulation time 43853032434 ps
CPU time 59.64 seconds
Started Apr 23 03:24:35 PM PDT 24
Finished Apr 23 03:25:35 PM PDT 24
Peak memory 216852 kb
Host smart-2a738561-5707-4fe7-9821-bf55bc655465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125046898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3125046898
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2670275979
Short name T275
Test name
Test status
Simulation time 72963382676 ps
CPU time 27.74 seconds
Started Apr 23 03:14:04 PM PDT 24
Finished Apr 23 03:14:32 PM PDT 24
Peak memory 227328 kb
Host smart-870a16ea-f4f6-4f1d-aa33-d4e69bfda4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670275979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2670275979
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3604142524
Short name T267
Test name
Test status
Simulation time 2965755847 ps
CPU time 28.5 seconds
Started Apr 23 03:17:45 PM PDT 24
Finished Apr 23 03:18:14 PM PDT 24
Peak memory 228904 kb
Host smart-d0143a17-9b13-4c9f-853b-2fe31035dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604142524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3604142524
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3387935494
Short name T252
Test name
Test status
Simulation time 9567909419 ps
CPU time 10.71 seconds
Started Apr 23 03:18:12 PM PDT 24
Finished Apr 23 03:18:23 PM PDT 24
Peak memory 219304 kb
Host smart-0d4f04df-c54b-4807-b253-b95b18f1b57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387935494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3387935494
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4260779227
Short name T294
Test name
Test status
Simulation time 560744540 ps
CPU time 20.88 seconds
Started Apr 23 03:19:38 PM PDT 24
Finished Apr 23 03:20:00 PM PDT 24
Peak memory 233112 kb
Host smart-024d83a5-ee40-43f4-a69a-e18b80bde32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260779227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4260779227
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.927715752
Short name T332
Test name
Test status
Simulation time 1396059294 ps
CPU time 8.83 seconds
Started Apr 23 03:19:39 PM PDT 24
Finished Apr 23 03:19:49 PM PDT 24
Peak memory 223192 kb
Host smart-457d5009-c627-4261-9f07-993bf6ee7f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927715752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.927715752
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3525318676
Short name T66
Test name
Test status
Simulation time 8601969980 ps
CPU time 23.3 seconds
Started Apr 23 03:19:35 PM PDT 24
Finished Apr 23 03:19:59 PM PDT 24
Peak memory 233316 kb
Host smart-48306ab7-2ead-4209-bdc1-dff8d8ebb6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525318676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3525318676
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4069837974
Short name T30
Test name
Test status
Simulation time 61178583 ps
CPU time 0.73 seconds
Started Apr 23 03:18:23 PM PDT 24
Finished Apr 23 03:18:25 PM PDT 24
Peak memory 206316 kb
Host smart-0fa2cb31-f854-41d8-b63f-54fa02aca45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069837974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4069837974
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3405242003
Short name T320
Test name
Test status
Simulation time 1661752648 ps
CPU time 10.78 seconds
Started Apr 23 03:18:25 PM PDT 24
Finished Apr 23 03:18:36 PM PDT 24
Peak memory 230148 kb
Host smart-b711cc89-79d1-49fd-b557-1247015b10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405242003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3405242003
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_intercept.943343362
Short name T245
Test name
Test status
Simulation time 656537211 ps
CPU time 8.72 seconds
Started Apr 23 03:20:08 PM PDT 24
Finished Apr 23 03:20:18 PM PDT 24
Peak memory 219032 kb
Host smart-bb944038-518f-4bca-8d4e-d0572075d353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943343362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.943343362
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_upload.3956342175
Short name T362
Test name
Test status
Simulation time 4630570005 ps
CPU time 9.3 seconds
Started Apr 23 03:20:28 PM PDT 24
Finished Apr 23 03:20:38 PM PDT 24
Peak memory 233356 kb
Host smart-e87c2e03-3f87-4f60-a6f9-bacbaa9f11f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956342175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3956342175
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2480173540
Short name T359
Test name
Test status
Simulation time 933225212 ps
CPU time 20.8 seconds
Started Apr 23 03:15:26 PM PDT 24
Finished Apr 23 03:15:47 PM PDT 24
Peak memory 224972 kb
Host smart-e2bb1ae5-a498-4623-b06f-19c61276b2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480173540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2480173540
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3111154783
Short name T176
Test name
Test status
Simulation time 5779432288 ps
CPU time 10.93 seconds
Started Apr 23 03:18:59 PM PDT 24
Finished Apr 23 03:19:10 PM PDT 24
Peak memory 225008 kb
Host smart-23a0cc71-ddda-485e-bd6f-af916b5ee606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111154783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3111154783
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1234144200
Short name T369
Test name
Test status
Simulation time 3315848764 ps
CPU time 12.42 seconds
Started Apr 23 02:44:52 PM PDT 24
Finished Apr 23 02:45:05 PM PDT 24
Peak memory 215352 kb
Host smart-4ef0a9b2-0440-44cc-84af-53d1156a4135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234144200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1234144200
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_intercept.892581952
Short name T289
Test name
Test status
Simulation time 9390738569 ps
CPU time 39.1 seconds
Started Apr 23 03:16:45 PM PDT 24
Finished Apr 23 03:17:25 PM PDT 24
Peak memory 223352 kb
Host smart-b4969eb2-e0e4-48ed-b8cc-8066b3d33c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892581952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.892581952
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3860036620
Short name T358
Test name
Test status
Simulation time 76385364296 ps
CPU time 25.96 seconds
Started Apr 23 03:18:28 PM PDT 24
Finished Apr 23 03:18:54 PM PDT 24
Peak memory 240392 kb
Host smart-d2d9de5d-f4b4-41e8-850c-1fcf33772573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860036620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3860036620
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2607307225
Short name T185
Test name
Test status
Simulation time 86903825482 ps
CPU time 50.91 seconds
Started Apr 23 03:19:46 PM PDT 24
Finished Apr 23 03:20:38 PM PDT 24
Peak memory 231044 kb
Host smart-587b4769-77a2-4ad8-b267-ffb8e9edeb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607307225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2607307225
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2891343633
Short name T236
Test name
Test status
Simulation time 1897625904 ps
CPU time 8.72 seconds
Started Apr 23 03:20:41 PM PDT 24
Finished Apr 23 03:20:50 PM PDT 24
Peak memory 241140 kb
Host smart-7056e039-bf57-47ad-8872-faae9d7afec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891343633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2891343633
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1831257952
Short name T69
Test name
Test status
Simulation time 3332490935 ps
CPU time 9.82 seconds
Started Apr 23 03:21:20 PM PDT 24
Finished Apr 23 03:21:30 PM PDT 24
Peak memory 219580 kb
Host smart-b6ccc7a3-6d0a-4343-82c9-ecfd824d85e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831257952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1831257952
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2699578173
Short name T91
Test name
Test status
Simulation time 1779077797 ps
CPU time 7.49 seconds
Started Apr 23 03:15:20 PM PDT 24
Finished Apr 23 03:15:28 PM PDT 24
Peak memory 224952 kb
Host smart-c37a528b-666a-4c8f-b4b0-531e74bb0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699578173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2699578173
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2551533436
Short name T115
Test name
Test status
Simulation time 20208780948 ps
CPU time 38.67 seconds
Started Apr 23 03:16:47 PM PDT 24
Finished Apr 23 03:17:26 PM PDT 24
Peak memory 227192 kb
Host smart-d747ec6d-4b84-48ef-8922-f7339cf6a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551533436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2551533436
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1987647178
Short name T210
Test name
Test status
Simulation time 380617390 ps
CPU time 3.74 seconds
Started Apr 23 03:17:16 PM PDT 24
Finished Apr 23 03:17:21 PM PDT 24
Peak memory 233144 kb
Host smart-df57a58b-83ee-4213-84aa-319fbc352b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987647178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1987647178
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2562668775
Short name T694
Test name
Test status
Simulation time 20866820493 ps
CPU time 68.38 seconds
Started Apr 23 03:17:36 PM PDT 24
Finished Apr 23 03:18:45 PM PDT 24
Peak memory 216904 kb
Host smart-4c48c723-007d-445e-beb5-a4f91fddbd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562668775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2562668775
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1877525879
Short name T319
Test name
Test status
Simulation time 496221348 ps
CPU time 7.74 seconds
Started Apr 23 03:18:27 PM PDT 24
Finished Apr 23 03:18:36 PM PDT 24
Peak memory 233312 kb
Host smart-05eca8ea-c66f-446e-af9c-0c2368c26908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877525879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1877525879
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3109098971
Short name T261
Test name
Test status
Simulation time 595443713 ps
CPU time 4.03 seconds
Started Apr 23 03:18:58 PM PDT 24
Finished Apr 23 03:19:02 PM PDT 24
Peak memory 219016 kb
Host smart-1d20126a-6797-4985-9996-cce71040842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109098971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3109098971
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_upload.518182517
Short name T10
Test name
Test status
Simulation time 7528778633 ps
CPU time 12.75 seconds
Started Apr 23 03:19:18 PM PDT 24
Finished Apr 23 03:19:31 PM PDT 24
Peak memory 234860 kb
Host smart-073c7ff8-4a54-4be9-a8e4-53344a646d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518182517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.518182517
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2652250273
Short name T256
Test name
Test status
Simulation time 11912998258 ps
CPU time 24.98 seconds
Started Apr 23 03:22:28 PM PDT 24
Finished Apr 23 03:22:54 PM PDT 24
Peak memory 219080 kb
Host smart-329bb840-6d79-4e0f-b304-d2de45631f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652250273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2652250273
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3083608980
Short name T355
Test name
Test status
Simulation time 151021206 ps
CPU time 1.02 seconds
Started Apr 23 03:25:00 PM PDT 24
Finished Apr 23 03:25:02 PM PDT 24
Peak memory 207828 kb
Host smart-fe273e30-0e8c-4313-8ef2-fd6b2743a587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083608980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3083608980
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1689477776
Short name T286
Test name
Test status
Simulation time 22714225599 ps
CPU time 21.15 seconds
Started Apr 23 03:16:28 PM PDT 24
Finished Apr 23 03:16:50 PM PDT 24
Peak memory 225080 kb
Host smart-bedde6f4-fbe4-4143-928d-ae88fb294f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689477776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1689477776
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_upload.1430583272
Short name T250
Test name
Test status
Simulation time 27669348880 ps
CPU time 17.37 seconds
Started Apr 23 03:14:44 PM PDT 24
Finished Apr 23 03:15:02 PM PDT 24
Peak memory 233236 kb
Host smart-94782521-5ce7-4449-84a1-e1cdca587334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430583272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1430583272
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.915417307
Short name T64
Test name
Test status
Simulation time 1254525400 ps
CPU time 11 seconds
Started Apr 23 03:16:45 PM PDT 24
Finished Apr 23 03:16:57 PM PDT 24
Peak memory 233376 kb
Host smart-e400ba23-8888-4623-98ad-b225148ff52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915417307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.915417307
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2225130532
Short name T70
Test name
Test status
Simulation time 14587695755 ps
CPU time 22.44 seconds
Started Apr 23 03:16:59 PM PDT 24
Finished Apr 23 03:17:22 PM PDT 24
Peak memory 223208 kb
Host smart-d83fd36b-b588-4df2-b943-de3070821914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225130532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2225130532
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_upload.2991412119
Short name T244
Test name
Test status
Simulation time 105983947 ps
CPU time 2.68 seconds
Started Apr 23 03:16:58 PM PDT 24
Finished Apr 23 03:17:01 PM PDT 24
Peak memory 223876 kb
Host smart-7392e2fa-5990-449f-afa3-19b0e63b30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991412119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2991412119
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3012009777
Short name T330
Test name
Test status
Simulation time 27712907507 ps
CPU time 62.81 seconds
Started Apr 23 03:17:20 PM PDT 24
Finished Apr 23 03:18:23 PM PDT 24
Peak memory 235484 kb
Host smart-f882d50a-4951-4fc3-92f6-68fde3d8daf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012009777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3012009777
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2293306269
Short name T323
Test name
Test status
Simulation time 350572936 ps
CPU time 2.59 seconds
Started Apr 23 03:17:43 PM PDT 24
Finished Apr 23 03:17:46 PM PDT 24
Peak memory 219368 kb
Host smart-e719f377-e043-4899-b96b-c58412267d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293306269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2293306269
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1954648682
Short name T206
Test name
Test status
Simulation time 6131938937 ps
CPU time 24.87 seconds
Started Apr 23 03:17:59 PM PDT 24
Finished Apr 23 03:18:24 PM PDT 24
Peak memory 223168 kb
Host smart-fd809f84-4c7a-4418-a58f-f64a8ffe3efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954648682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1954648682
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_upload.10614407
Short name T344
Test name
Test status
Simulation time 835879439 ps
CPU time 4.61 seconds
Started Apr 23 03:18:49 PM PDT 24
Finished Apr 23 03:18:54 PM PDT 24
Peak memory 216808 kb
Host smart-cc5d302f-15b6-40a1-b910-e12e64b692fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10614407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.10614407
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3345344811
Short name T73
Test name
Test status
Simulation time 25270338559 ps
CPU time 35.6 seconds
Started Apr 23 03:19:30 PM PDT 24
Finished Apr 23 03:20:05 PM PDT 24
Peak memory 225428 kb
Host smart-060b0701-be15-4edb-90ef-40a050236c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345344811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3345344811
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2701158096
Short name T74
Test name
Test status
Simulation time 860749749 ps
CPU time 5.71 seconds
Started Apr 23 03:19:57 PM PDT 24
Finished Apr 23 03:20:03 PM PDT 24
Peak memory 223776 kb
Host smart-10e0a3db-a20d-4be1-afbf-85e4d77a5d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701158096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2701158096
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1245398
Short name T201
Test name
Test status
Simulation time 1242654587 ps
CPU time 3.72 seconds
Started Apr 23 03:19:58 PM PDT 24
Finished Apr 23 03:20:02 PM PDT 24
Peak memory 223712 kb
Host smart-5ee4b9d2-0390-4195-b9ba-d391c699a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1245398
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1294653616
Short name T272
Test name
Test status
Simulation time 1983191543 ps
CPU time 11.84 seconds
Started Apr 23 03:21:01 PM PDT 24
Finished Apr 23 03:21:14 PM PDT 24
Peak memory 223416 kb
Host smart-d7e17b85-933f-4ec5-9020-62262e1ee35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294653616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1294653616
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2901928523
Short name T239
Test name
Test status
Simulation time 329024649 ps
CPU time 5.98 seconds
Started Apr 23 03:15:13 PM PDT 24
Finished Apr 23 03:15:20 PM PDT 24
Peak memory 219320 kb
Host smart-97bf3397-d591-43a7-ac87-867d696a55d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901928523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2901928523
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.87521685
Short name T197
Test name
Test status
Simulation time 331147835 ps
CPU time 3.53 seconds
Started Apr 23 03:15:13 PM PDT 24
Finished Apr 23 03:15:17 PM PDT 24
Peak memory 223316 kb
Host smart-81645d11-b1ed-4d3f-af64-4aa089fe45f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87521685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.87521685
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1490416875
Short name T86
Test name
Test status
Simulation time 192367477 ps
CPU time 3.98 seconds
Started Apr 23 03:21:26 PM PDT 24
Finished Apr 23 03:21:30 PM PDT 24
Peak memory 218872 kb
Host smart-c1a973b5-45f2-4f3b-815c-35944cf2830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490416875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1490416875
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1778706185
Short name T265
Test name
Test status
Simulation time 3225684542 ps
CPU time 8.97 seconds
Started Apr 23 03:22:52 PM PDT 24
Finished Apr 23 03:23:01 PM PDT 24
Peak memory 219216 kb
Host smart-23b86566-8891-4c7a-98e2-00d8dec26ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778706185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1778706185
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1353441307
Short name T232
Test name
Test status
Simulation time 6953599130 ps
CPU time 25.61 seconds
Started Apr 23 03:23:09 PM PDT 24
Finished Apr 23 03:23:35 PM PDT 24
Peak memory 225052 kb
Host smart-1e1da00d-0816-4317-bf86-cd09d74ddb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353441307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1353441307
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1104123206
Short name T202
Test name
Test status
Simulation time 4841023688 ps
CPU time 5.71 seconds
Started Apr 23 03:24:03 PM PDT 24
Finished Apr 23 03:24:09 PM PDT 24
Peak memory 217352 kb
Host smart-0ba28cf5-5427-4959-b17e-c81b082b3456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104123206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1104123206
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_intercept.487970726
Short name T693
Test name
Test status
Simulation time 132021614 ps
CPU time 2.59 seconds
Started Apr 23 03:16:08 PM PDT 24
Finished Apr 23 03:16:12 PM PDT 24
Peak memory 222660 kb
Host smart-c049f0a1-14f3-462b-9d62-114c805b2794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487970726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.487970726
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4086458128
Short name T293
Test name
Test status
Simulation time 11878911698 ps
CPU time 141.77 seconds
Started Apr 23 03:16:32 PM PDT 24
Finished Apr 23 03:18:54 PM PDT 24
Peak memory 252724 kb
Host smart-5b9eec15-f8db-4001-8c24-4d2aa4376d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086458128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4086458128
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.990806731
Short name T779
Test name
Test status
Simulation time 578873213 ps
CPU time 19.67 seconds
Started Apr 23 02:44:14 PM PDT 24
Finished Apr 23 02:44:34 PM PDT 24
Peak memory 215344 kb
Host smart-a24f01b2-0d4d-4283-85db-8bdad9eb77a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990806731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.990806731
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3640860015
Short name T352
Test name
Test status
Simulation time 7079990552 ps
CPU time 18.55 seconds
Started Apr 23 03:14:06 PM PDT 24
Finished Apr 23 03:14:25 PM PDT 24
Peak memory 236532 kb
Host smart-62bfbeda-d206-44ac-b424-004f9aab7d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640860015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3640860015
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1511005276
Short name T56
Test name
Test status
Simulation time 5563330430 ps
CPU time 19.1 seconds
Started Apr 23 03:14:02 PM PDT 24
Finished Apr 23 03:14:21 PM PDT 24
Peak memory 217008 kb
Host smart-03bd1c72-aee8-4bd2-ac0a-ff85cb141335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511005276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1511005276
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_upload.4189470696
Short name T199
Test name
Test status
Simulation time 2936958548 ps
CPU time 5.8 seconds
Started Apr 23 03:14:14 PM PDT 24
Finished Apr 23 03:14:20 PM PDT 24
Peak memory 221312 kb
Host smart-218c4097-f9cd-40c5-8e2d-da2cb1f64a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189470696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4189470696
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2681294379
Short name T295
Test name
Test status
Simulation time 216328791 ps
CPU time 11.97 seconds
Started Apr 23 03:14:43 PM PDT 24
Finished Apr 23 03:14:56 PM PDT 24
Peak memory 235660 kb
Host smart-e65c4b70-c358-46eb-bf76-87a4c1700e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681294379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2681294379
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.521049367
Short name T247
Test name
Test status
Simulation time 774907107 ps
CPU time 2.32 seconds
Started Apr 23 03:17:16 PM PDT 24
Finished Apr 23 03:17:19 PM PDT 24
Peak memory 217420 kb
Host smart-7afa2b94-d635-46cb-9200-7de56e1f50f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521049367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.521049367
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4006331618
Short name T221
Test name
Test status
Simulation time 1072977968 ps
CPU time 4.26 seconds
Started Apr 23 03:17:33 PM PDT 24
Finished Apr 23 03:17:38 PM PDT 24
Peak memory 219040 kb
Host smart-bfdc29a0-5736-4aec-b687-da73cfc7e089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006331618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4006331618
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3877936749
Short name T303
Test name
Test status
Simulation time 8720151329 ps
CPU time 79.15 seconds
Started Apr 23 03:17:31 PM PDT 24
Finished Apr 23 03:18:51 PM PDT 24
Peak memory 236732 kb
Host smart-cd3defbc-0dae-441b-aaa4-dd8458e58ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877936749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3877936749
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1746902757
Short name T346
Test name
Test status
Simulation time 21311609472 ps
CPU time 15.36 seconds
Started Apr 23 03:17:28 PM PDT 24
Finished Apr 23 03:17:44 PM PDT 24
Peak memory 233032 kb
Host smart-a31aa0f8-3ef2-45e5-830f-2fc892a18b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746902757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1746902757
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3737237781
Short name T304
Test name
Test status
Simulation time 32038847193 ps
CPU time 44.26 seconds
Started Apr 23 03:17:44 PM PDT 24
Finished Apr 23 03:18:29 PM PDT 24
Peak memory 252828 kb
Host smart-1d3c1840-8d36-4fde-93e6-0fadf0aa1415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737237781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3737237781
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2751797889
Short name T227
Test name
Test status
Simulation time 31124765329 ps
CPU time 21.47 seconds
Started Apr 23 03:17:44 PM PDT 24
Finished Apr 23 03:18:06 PM PDT 24
Peak memory 223908 kb
Host smart-2887be42-8024-4daa-a6a2-e3fe4f90fb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751797889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2751797889
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3916778224
Short name T301
Test name
Test status
Simulation time 48312565244 ps
CPU time 76.18 seconds
Started Apr 23 03:18:17 PM PDT 24
Finished Apr 23 03:19:34 PM PDT 24
Peak memory 249712 kb
Host smart-6087b8e7-b3da-4b76-9d87-96732fa4bb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916778224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3916778224
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1574424473
Short name T89
Test name
Test status
Simulation time 118982170 ps
CPU time 3.67 seconds
Started Apr 23 03:18:12 PM PDT 24
Finished Apr 23 03:18:16 PM PDT 24
Peak memory 223596 kb
Host smart-5ab62e37-8f4a-4c0d-8be7-809c88e872e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574424473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1574424473
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4193625019
Short name T259
Test name
Test status
Simulation time 8388751861 ps
CPU time 20.9 seconds
Started Apr 23 03:18:08 PM PDT 24
Finished Apr 23 03:18:29 PM PDT 24
Peak memory 239436 kb
Host smart-543d558e-06f1-4b3c-b88e-3c0ba1cefc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193625019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4193625019
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3897227395
Short name T331
Test name
Test status
Simulation time 364950374 ps
CPU time 8.97 seconds
Started Apr 23 03:18:29 PM PDT 24
Finished Apr 23 03:18:38 PM PDT 24
Peak memory 240740 kb
Host smart-9a2b1b48-2258-4026-9c92-3006a2029d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897227395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3897227395
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2826398881
Short name T340
Test name
Test status
Simulation time 2816560436 ps
CPU time 22.83 seconds
Started Apr 23 03:18:54 PM PDT 24
Finished Apr 23 03:19:17 PM PDT 24
Peak memory 219104 kb
Host smart-f8751155-5825-4ca5-8d47-e38559da353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826398881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2826398881
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2634479023
Short name T337
Test name
Test status
Simulation time 2384009593 ps
CPU time 21.74 seconds
Started Apr 23 03:18:58 PM PDT 24
Finished Apr 23 03:19:20 PM PDT 24
Peak memory 219024 kb
Host smart-51c954ca-bb1b-4fb1-9caa-8d7a2cee44bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634479023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2634479023
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2733826548
Short name T182
Test name
Test status
Simulation time 775858589 ps
CPU time 16.88 seconds
Started Apr 23 03:19:02 PM PDT 24
Finished Apr 23 03:19:19 PM PDT 24
Peak memory 241444 kb
Host smart-d073f3e7-794d-4975-a137-59951db6742d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733826548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2733826548
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3969658842
Short name T351
Test name
Test status
Simulation time 1580927217 ps
CPU time 6.87 seconds
Started Apr 23 03:14:50 PM PDT 24
Finished Apr 23 03:14:57 PM PDT 24
Peak memory 223464 kb
Host smart-228be4e9-50a7-4ee1-828b-48f3d2789585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969658842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3969658842
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_upload.762506649
Short name T214
Test name
Test status
Simulation time 3093405281 ps
CPU time 7.37 seconds
Started Apr 23 03:14:53 PM PDT 24
Finished Apr 23 03:15:01 PM PDT 24
Peak memory 233136 kb
Host smart-8512e202-863b-4709-a6ad-1bb40419bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762506649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.762506649
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4080228136
Short name T113
Test name
Test status
Simulation time 3250949309 ps
CPU time 36.04 seconds
Started Apr 23 03:19:26 PM PDT 24
Finished Apr 23 03:20:03 PM PDT 24
Peak memory 219536 kb
Host smart-3aeb2888-93c6-4079-bd00-41c799601615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080228136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4080228136
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_upload.4029577853
Short name T242
Test name
Test status
Simulation time 10912363359 ps
CPU time 10.79 seconds
Started Apr 23 03:19:30 PM PDT 24
Finished Apr 23 03:19:41 PM PDT 24
Peak memory 233640 kb
Host smart-164e4773-857b-48f4-afbd-46b6003a697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029577853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4029577853
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_upload.1489159407
Short name T213
Test name
Test status
Simulation time 779237038 ps
CPU time 5.17 seconds
Started Apr 23 03:19:36 PM PDT 24
Finished Apr 23 03:19:42 PM PDT 24
Peak memory 219248 kb
Host smart-892a8b46-5feb-4833-b8a5-492cda3b4ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489159407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1489159407
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1120969612
Short name T284
Test name
Test status
Simulation time 4658845760 ps
CPU time 13.26 seconds
Started Apr 23 03:19:51 PM PDT 24
Finished Apr 23 03:20:04 PM PDT 24
Peak memory 219452 kb
Host smart-690c337a-2d63-4cd3-8f1b-707ad533cb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120969612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1120969612
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_upload.3042783141
Short name T192
Test name
Test status
Simulation time 3888065344 ps
CPU time 12.92 seconds
Started Apr 23 03:19:51 PM PDT 24
Finished Apr 23 03:20:05 PM PDT 24
Peak memory 224308 kb
Host smart-bf83f540-4438-41d4-9776-217231c4672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042783141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3042783141
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3355502323
Short name T290
Test name
Test status
Simulation time 1135737686 ps
CPU time 6.06 seconds
Started Apr 23 03:20:09 PM PDT 24
Finished Apr 23 03:20:15 PM PDT 24
Peak memory 235420 kb
Host smart-ad224a02-aa7b-424e-a55e-dade590b828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355502323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3355502323
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3522678717
Short name T251
Test name
Test status
Simulation time 2586913911 ps
CPU time 7.78 seconds
Started Apr 23 03:20:22 PM PDT 24
Finished Apr 23 03:20:30 PM PDT 24
Peak memory 217364 kb
Host smart-41bc30e5-9a70-43d8-9f79-7eac2ca40b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522678717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3522678717
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1720130623
Short name T311
Test name
Test status
Simulation time 1212362408 ps
CPU time 7.33 seconds
Started Apr 23 03:20:20 PM PDT 24
Finished Apr 23 03:20:28 PM PDT 24
Peak memory 219024 kb
Host smart-875aa9f0-9fc5-4ed2-a295-0e52b3c32992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720130623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1720130623
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.560086711
Short name T207
Test name
Test status
Simulation time 54175529 ps
CPU time 2.26 seconds
Started Apr 23 03:20:35 PM PDT 24
Finished Apr 23 03:20:38 PM PDT 24
Peak memory 218900 kb
Host smart-bf6b82d0-236f-49e6-a9ba-90453d72f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560086711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.560086711
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3395227334
Short name T225
Test name
Test status
Simulation time 2414386490 ps
CPU time 13.69 seconds
Started Apr 23 03:15:12 PM PDT 24
Finished Apr 23 03:15:26 PM PDT 24
Peak memory 239352 kb
Host smart-adc0e43b-7334-4ecd-b7c4-a60b1e82f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395227334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3395227334
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3434737673
Short name T47
Test name
Test status
Simulation time 5712678073 ps
CPU time 15.78 seconds
Started Apr 23 03:21:22 PM PDT 24
Finished Apr 23 03:21:38 PM PDT 24
Peak memory 219092 kb
Host smart-ffeebe5c-8ca0-48cf-9f80-731098bddd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434737673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3434737673
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1729607341
Short name T335
Test name
Test status
Simulation time 1054358749 ps
CPU time 5.29 seconds
Started Apr 23 03:21:38 PM PDT 24
Finished Apr 23 03:21:44 PM PDT 24
Peak memory 219052 kb
Host smart-bae6b446-a7f4-41aa-ab33-9015447873d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729607341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1729607341
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1204392310
Short name T253
Test name
Test status
Simulation time 162257846 ps
CPU time 5.26 seconds
Started Apr 23 03:21:34 PM PDT 24
Finished Apr 23 03:21:40 PM PDT 24
Peak memory 219332 kb
Host smart-cb1d35e1-bae8-4352-b981-0214df2849f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204392310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1204392310
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2817759953
Short name T328
Test name
Test status
Simulation time 145526139 ps
CPU time 3.01 seconds
Started Apr 23 03:21:35 PM PDT 24
Finished Apr 23 03:21:38 PM PDT 24
Peak memory 219104 kb
Host smart-c2fd1340-dbdf-47e6-afd9-23dfc0eb4c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817759953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2817759953
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3087162838
Short name T173
Test name
Test status
Simulation time 5548230763 ps
CPU time 27.07 seconds
Started Apr 23 03:22:11 PM PDT 24
Finished Apr 23 03:22:38 PM PDT 24
Peak memory 219416 kb
Host smart-37e3794a-4f9e-4765-aa4f-53c847055561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087162838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3087162838
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1837857568
Short name T211
Test name
Test status
Simulation time 5429155630 ps
CPU time 6.22 seconds
Started Apr 23 03:22:07 PM PDT 24
Finished Apr 23 03:22:14 PM PDT 24
Peak memory 218012 kb
Host smart-f47f6958-fa6a-4bf5-be75-6a8b23628731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837857568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1837857568
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_upload.1307648319
Short name T234
Test name
Test status
Simulation time 512954217 ps
CPU time 2.92 seconds
Started Apr 23 03:22:18 PM PDT 24
Finished Apr 23 03:22:21 PM PDT 24
Peak memory 218260 kb
Host smart-9d37a049-5668-4347-808d-e620b955eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307648319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1307648319
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.43496358
Short name T273
Test name
Test status
Simulation time 32046001118 ps
CPU time 13.44 seconds
Started Apr 23 03:22:29 PM PDT 24
Finished Apr 23 03:22:43 PM PDT 24
Peak memory 223628 kb
Host smart-8c6e4087-a85e-4b5c-a6e8-e12ab0845e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43496358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.43496358
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1212009389
Short name T263
Test name
Test status
Simulation time 202233510 ps
CPU time 2.45 seconds
Started Apr 23 03:22:51 PM PDT 24
Finished Apr 23 03:22:54 PM PDT 24
Peak memory 219200 kb
Host smart-089fa452-ecd9-4d4c-9ac1-141a11c9d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212009389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1212009389
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_upload.1721718859
Short name T309
Test name
Test status
Simulation time 2477479183 ps
CPU time 5.44 seconds
Started Apr 23 03:22:56 PM PDT 24
Finished Apr 23 03:23:02 PM PDT 24
Peak memory 216900 kb
Host smart-29e146da-7612-46d5-8a90-b5ff79e73876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721718859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1721718859
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.2510961122
Short name T203
Test name
Test status
Simulation time 706179899 ps
CPU time 9.15 seconds
Started Apr 23 03:15:24 PM PDT 24
Finished Apr 23 03:15:34 PM PDT 24
Peak memory 240536 kb
Host smart-715ef96c-eb60-4afa-a3df-bfd3c2b5f47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510961122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2510961122
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2435791566
Short name T316
Test name
Test status
Simulation time 1354318544 ps
CPU time 11.73 seconds
Started Apr 23 03:23:08 PM PDT 24
Finished Apr 23 03:23:21 PM PDT 24
Peak memory 221824 kb
Host smart-b175600a-cc57-4bfa-884d-a7bde78c2019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435791566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2435791566
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1736264762
Short name T348
Test name
Test status
Simulation time 6383193204 ps
CPU time 12.59 seconds
Started Apr 23 03:23:14 PM PDT 24
Finished Apr 23 03:23:27 PM PDT 24
Peak memory 233284 kb
Host smart-f2ee6a2b-9135-41d9-9e7c-7710b5839116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736264762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1736264762
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_upload.732876475
Short name T240
Test name
Test status
Simulation time 387810392 ps
CPU time 5.08 seconds
Started Apr 23 03:23:23 PM PDT 24
Finished Apr 23 03:23:29 PM PDT 24
Peak memory 223820 kb
Host smart-00809992-b0dc-45f9-82f4-e5349dfd23f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732876475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.732876475
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1877265732
Short name T109
Test name
Test status
Simulation time 4209056441 ps
CPU time 13.01 seconds
Started Apr 23 03:23:32 PM PDT 24
Finished Apr 23 03:23:45 PM PDT 24
Peak memory 224172 kb
Host smart-5aa09861-dfb3-4127-88e6-9b6a4f3d83f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877265732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1877265732
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1294938958
Short name T281
Test name
Test status
Simulation time 7546787290 ps
CPU time 8.3 seconds
Started Apr 23 03:23:31 PM PDT 24
Finished Apr 23 03:23:40 PM PDT 24
Peak memory 217492 kb
Host smart-49fbeff5-69e9-49c8-84c5-10d7fef00e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294938958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1294938958
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3546467904
Short name T322
Test name
Test status
Simulation time 2296490298 ps
CPU time 13.98 seconds
Started Apr 23 03:23:43 PM PDT 24
Finished Apr 23 03:23:58 PM PDT 24
Peak memory 224216 kb
Host smart-4e156c7b-7cfa-4672-a5b9-4458df34942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546467904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3546467904
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4118266539
Short name T60
Test name
Test status
Simulation time 28745164760 ps
CPU time 14.15 seconds
Started Apr 23 03:23:55 PM PDT 24
Finished Apr 23 03:24:10 PM PDT 24
Peak memory 224984 kb
Host smart-73a3b1ad-f1a2-45d0-a012-8722c501594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118266539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4118266539
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1440117871
Short name T246
Test name
Test status
Simulation time 2662921062 ps
CPU time 6.83 seconds
Started Apr 23 03:24:16 PM PDT 24
Finished Apr 23 03:24:23 PM PDT 24
Peak memory 221000 kb
Host smart-f0c4a167-82a6-4611-9225-2a59c9b89e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440117871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1440117871
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3768574314
Short name T72
Test name
Test status
Simulation time 903453283 ps
CPU time 5.09 seconds
Started Apr 23 03:24:14 PM PDT 24
Finished Apr 23 03:24:19 PM PDT 24
Peak memory 219200 kb
Host smart-d50406df-9c63-49b2-a62a-0e743bad5c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768574314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3768574314
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3919434491
Short name T11
Test name
Test status
Simulation time 2253279537 ps
CPU time 5.42 seconds
Started Apr 23 03:24:23 PM PDT 24
Finished Apr 23 03:24:29 PM PDT 24
Peak memory 219308 kb
Host smart-1381966c-87cf-4881-ad69-212cba3a14e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919434491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3919434491
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2831970420
Short name T363
Test name
Test status
Simulation time 8622990204 ps
CPU time 7.09 seconds
Started Apr 23 03:24:44 PM PDT 24
Finished Apr 23 03:24:51 PM PDT 24
Peak memory 217332 kb
Host smart-c7d7c0b7-ed64-44ed-8142-34bb5173eb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831970420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2831970420
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1529243269
Short name T187
Test name
Test status
Simulation time 415764864 ps
CPU time 3.03 seconds
Started Apr 23 03:15:34 PM PDT 24
Finished Apr 23 03:15:38 PM PDT 24
Peak memory 219008 kb
Host smart-b6cd3318-da83-411f-92fa-6560275ba177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529243269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1529243269
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1662301322
Short name T205
Test name
Test status
Simulation time 172087653 ps
CPU time 3.02 seconds
Started Apr 23 03:15:50 PM PDT 24
Finished Apr 23 03:15:54 PM PDT 24
Peak memory 223708 kb
Host smart-a43ee1ac-675d-4145-ab6d-9b96f056ccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662301322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1662301322
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.860649185
Short name T336
Test name
Test status
Simulation time 3951494573 ps
CPU time 20.09 seconds
Started Apr 23 03:15:49 PM PDT 24
Finished Apr 23 03:16:09 PM PDT 24
Peak memory 222956 kb
Host smart-8f8a2426-95c2-4544-9191-e36a9cebffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860649185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.860649185
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3591569708
Short name T191
Test name
Test status
Simulation time 1801745988 ps
CPU time 11.04 seconds
Started Apr 23 03:16:10 PM PDT 24
Finished Apr 23 03:16:21 PM PDT 24
Peak memory 238780 kb
Host smart-6fbc1b96-0036-47bf-baa2-7b374c6ff3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591569708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3591569708
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2841896275
Short name T350
Test name
Test status
Simulation time 18854334410 ps
CPU time 11.55 seconds
Started Apr 23 03:16:32 PM PDT 24
Finished Apr 23 03:16:44 PM PDT 24
Peak memory 219152 kb
Host smart-c36aa3d4-03e9-4341-a608-2af80a34465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841896275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2841896275
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3347908111
Short name T95
Test name
Test status
Simulation time 115458272 ps
CPU time 1.21 seconds
Started Apr 23 02:44:17 PM PDT 24
Finished Apr 23 02:44:19 PM PDT 24
Peak memory 207028 kb
Host smart-8a6be6d6-e32c-417d-b851-8c2c9fd12b69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347908111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3347908111
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2998995978
Short name T85
Test name
Test status
Simulation time 389630977 ps
CPU time 3.63 seconds
Started Apr 23 03:21:11 PM PDT 24
Finished Apr 23 03:21:15 PM PDT 24
Peak memory 219024 kb
Host smart-36d5e1bf-dcd5-4338-9d3a-8b53e7ec1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998995978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2998995978
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.591221657
Short name T140
Test name
Test status
Simulation time 230016379 ps
CPU time 14.99 seconds
Started Apr 23 02:44:15 PM PDT 24
Finished Apr 23 02:44:31 PM PDT 24
Peak memory 206992 kb
Host smart-f09f8f54-d368-4f44-9e3c-2bea4be960b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591221657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.591221657
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1125525249
Short name T146
Test name
Test status
Simulation time 185088823 ps
CPU time 11.06 seconds
Started Apr 23 02:44:13 PM PDT 24
Finished Apr 23 02:44:25 PM PDT 24
Peak memory 207048 kb
Host smart-b8b14f49-d6e5-4c8b-8132-d7221cc77e89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125525249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1125525249
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.959797009
Short name T94
Test name
Test status
Simulation time 33171900 ps
CPU time 1.18 seconds
Started Apr 23 02:44:12 PM PDT 24
Finished Apr 23 02:44:13 PM PDT 24
Peak memory 216252 kb
Host smart-07f4f5f9-6367-4614-84b3-a362b502b3b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959797009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.959797009
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.164636198
Short name T111
Test name
Test status
Simulation time 93686090 ps
CPU time 1.68 seconds
Started Apr 23 02:44:15 PM PDT 24
Finished Apr 23 02:44:17 PM PDT 24
Peak memory 215512 kb
Host smart-f092653c-44a2-4bb3-8397-b2d2ab1be78f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164636198 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.164636198
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2048617201
Short name T818
Test name
Test status
Simulation time 55975344 ps
CPU time 0.68 seconds
Started Apr 23 02:44:11 PM PDT 24
Finished Apr 23 02:44:12 PM PDT 24
Peak memory 203540 kb
Host smart-446fc8fa-2d87-47df-8d89-416edab4a90c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048617201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
048617201
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.22219650
Short name T808
Test name
Test status
Simulation time 105293370 ps
CPU time 2.04 seconds
Started Apr 23 02:44:13 PM PDT 24
Finished Apr 23 02:44:15 PM PDT 24
Peak memory 215284 kb
Host smart-025663c5-2f9d-491e-9c9f-1bdbd23ff4a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22219650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_d
evice_mem_partial_access.22219650
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1436346721
Short name T769
Test name
Test status
Simulation time 20326546 ps
CPU time 0.67 seconds
Started Apr 23 02:44:11 PM PDT 24
Finished Apr 23 02:44:12 PM PDT 24
Peak memory 203500 kb
Host smart-57d77ae1-29c5-4880-bb76-c2e822371874
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436346721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1436346721
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2555464345
Short name T804
Test name
Test status
Simulation time 621505772 ps
CPU time 4.37 seconds
Started Apr 23 02:44:15 PM PDT 24
Finished Apr 23 02:44:20 PM PDT 24
Peak memory 215204 kb
Host smart-bdba52a7-50bd-4156-a560-17f82e5d78bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555464345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2555464345
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.946424761
Short name T123
Test name
Test status
Simulation time 710951394 ps
CPU time 4.7 seconds
Started Apr 23 02:44:08 PM PDT 24
Finished Apr 23 02:44:13 PM PDT 24
Peak memory 215564 kb
Host smart-594c68e1-751e-46a7-a269-8c100ef110eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946424761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.946424761
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1035489686
Short name T35
Test name
Test status
Simulation time 211137372 ps
CPU time 12.55 seconds
Started Apr 23 02:44:13 PM PDT 24
Finished Apr 23 02:44:25 PM PDT 24
Peak memory 216332 kb
Host smart-6238ed8c-6791-4d77-9e15-fee3b1702f96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035489686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1035489686
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.864549398
Short name T144
Test name
Test status
Simulation time 683565033 ps
CPU time 7.99 seconds
Started Apr 23 02:44:21 PM PDT 24
Finished Apr 23 02:44:29 PM PDT 24
Peak memory 207092 kb
Host smart-b50fbf70-5ea3-40e0-8c96-b292fc1b25ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864549398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.864549398
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3478980457
Short name T795
Test name
Test status
Simulation time 1976456939 ps
CPU time 12.96 seconds
Started Apr 23 02:44:16 PM PDT 24
Finished Apr 23 02:44:29 PM PDT 24
Peak memory 207068 kb
Host smart-b1028c0b-d927-45f1-b6ef-c8c3db1c69a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478980457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3478980457
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2991737808
Short name T784
Test name
Test status
Simulation time 199146167 ps
CPU time 3.42 seconds
Started Apr 23 02:44:21 PM PDT 24
Finished Apr 23 02:44:25 PM PDT 24
Peak memory 217132 kb
Host smart-4810c631-0ea9-4fca-8efe-6055c2b7e0fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991737808 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2991737808
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2533256257
Short name T731
Test name
Test status
Simulation time 21561962 ps
CPU time 1.21 seconds
Started Apr 23 02:44:16 PM PDT 24
Finished Apr 23 02:44:18 PM PDT 24
Peak memory 215188 kb
Host smart-f9536210-97b6-45f2-8ed9-d7efdd983766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533256257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
533256257
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.319108097
Short name T728
Test name
Test status
Simulation time 12890213 ps
CPU time 0.69 seconds
Started Apr 23 02:44:16 PM PDT 24
Finished Apr 23 02:44:17 PM PDT 24
Peak memory 203868 kb
Host smart-299115b2-ba5c-4bc3-b5bd-54d15bfcb586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319108097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.319108097
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2341767734
Short name T829
Test name
Test status
Simulation time 211149878 ps
CPU time 1.78 seconds
Started Apr 23 02:44:16 PM PDT 24
Finished Apr 23 02:44:18 PM PDT 24
Peak memory 215324 kb
Host smart-8d7c95a4-7fd2-4fa9-92cb-d3a56e3a3ea5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341767734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2341767734
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3983973943
Short name T751
Test name
Test status
Simulation time 13703461 ps
CPU time 0.65 seconds
Started Apr 23 02:44:16 PM PDT 24
Finished Apr 23 02:44:17 PM PDT 24
Peak memory 203520 kb
Host smart-8c7c045e-337f-45e3-8ea4-8ee948c01c2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983973943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3983973943
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1694385943
Short name T157
Test name
Test status
Simulation time 237999351 ps
CPU time 4.01 seconds
Started Apr 23 02:44:21 PM PDT 24
Finished Apr 23 02:44:25 PM PDT 24
Peak memory 207000 kb
Host smart-4518f5c3-c908-402c-a3c7-90a4bf290587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694385943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1694385943
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3850888191
Short name T122
Test name
Test status
Simulation time 64362034 ps
CPU time 2.05 seconds
Started Apr 23 02:44:15 PM PDT 24
Finished Apr 23 02:44:18 PM PDT 24
Peak memory 215528 kb
Host smart-fcbe7e93-707a-4b8d-bdfb-cb28295e1c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850888191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
850888191
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.756628801
Short name T743
Test name
Test status
Simulation time 91462898 ps
CPU time 1.79 seconds
Started Apr 23 02:44:59 PM PDT 24
Finished Apr 23 02:45:01 PM PDT 24
Peak memory 216392 kb
Host smart-da0949ef-a784-415e-a083-449c2a4c881d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756628801 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.756628801
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.914442835
Short name T141
Test name
Test status
Simulation time 94293868 ps
CPU time 2.54 seconds
Started Apr 23 02:44:55 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 215228 kb
Host smart-75ee4733-1b63-4cae-a366-bec7aff32547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914442835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.914442835
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3634131340
Short name T748
Test name
Test status
Simulation time 20908482 ps
CPU time 0.8 seconds
Started Apr 23 02:44:57 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 203568 kb
Host smart-92940de0-df10-47f5-9cb0-8b026cd80ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634131340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3634131340
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2985958059
Short name T780
Test name
Test status
Simulation time 27217011 ps
CPU time 1.72 seconds
Started Apr 23 02:44:58 PM PDT 24
Finished Apr 23 02:45:00 PM PDT 24
Peak memory 207020 kb
Host smart-0592524b-d5ff-4e74-bc4b-ca22e6e1d026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985958059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2985958059
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2469525086
Short name T767
Test name
Test status
Simulation time 177973625 ps
CPU time 2.81 seconds
Started Apr 23 02:44:55 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 215392 kb
Host smart-2135717b-a83f-478f-a581-87c9ad835220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469525086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2469525086
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1846120875
Short name T135
Test name
Test status
Simulation time 294218298 ps
CPU time 7.6 seconds
Started Apr 23 02:44:59 PM PDT 24
Finished Apr 23 02:45:07 PM PDT 24
Peak memory 215268 kb
Host smart-34d9ac81-e36f-4a89-8650-7a5f2b44292d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846120875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1846120875
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1683783175
Short name T776
Test name
Test status
Simulation time 38254373 ps
CPU time 2.45 seconds
Started Apr 23 02:44:56 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 216384 kb
Host smart-3729ba83-84a8-4df5-afed-b85603507ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683783175 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1683783175
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2909981727
Short name T145
Test name
Test status
Simulation time 245816625 ps
CPU time 2.07 seconds
Started Apr 23 02:44:57 PM PDT 24
Finished Apr 23 02:44:59 PM PDT 24
Peak memory 215216 kb
Host smart-0d86761a-b8dd-4e54-8a26-003b4d9cfbd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909981727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2909981727
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1859970138
Short name T828
Test name
Test status
Simulation time 11283680 ps
CPU time 0.71 seconds
Started Apr 23 02:44:57 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 203880 kb
Host smart-ba229f66-2ada-4a17-a3a2-b8e0f747de54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859970138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1859970138
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2799246947
Short name T790
Test name
Test status
Simulation time 61588027 ps
CPU time 1.9 seconds
Started Apr 23 02:44:58 PM PDT 24
Finished Apr 23 02:45:00 PM PDT 24
Peak memory 206968 kb
Host smart-335b0f8b-bccc-473b-8d93-69f7a1619087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799246947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2799246947
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.956751034
Short name T792
Test name
Test status
Simulation time 197271728 ps
CPU time 3.8 seconds
Started Apr 23 02:44:56 PM PDT 24
Finished Apr 23 02:45:00 PM PDT 24
Peak memory 215600 kb
Host smart-f0c454a5-9558-4a39-bb68-86d3724af373
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956751034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.956751034
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2486952555
Short name T817
Test name
Test status
Simulation time 418936351 ps
CPU time 6.45 seconds
Started Apr 23 02:44:58 PM PDT 24
Finished Apr 23 02:45:05 PM PDT 24
Peak memory 215412 kb
Host smart-7e9db7ef-6e84-4727-924d-dbdd731773a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486952555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2486952555
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.94410180
Short name T806
Test name
Test status
Simulation time 192169184 ps
CPU time 4.04 seconds
Started Apr 23 02:45:00 PM PDT 24
Finished Apr 23 02:45:04 PM PDT 24
Peak memory 217980 kb
Host smart-374babfd-632f-4b26-852f-9480aec78c8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94410180 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.94410180
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2216929581
Short name T139
Test name
Test status
Simulation time 156504845 ps
CPU time 2.01 seconds
Started Apr 23 02:45:01 PM PDT 24
Finished Apr 23 02:45:03 PM PDT 24
Peak memory 207000 kb
Host smart-577be32b-d205-4563-810f-e56936d6d10d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216929581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2216929581
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4209267064
Short name T735
Test name
Test status
Simulation time 46307616 ps
CPU time 0.76 seconds
Started Apr 23 02:45:04 PM PDT 24
Finished Apr 23 02:45:05 PM PDT 24
Peak memory 203648 kb
Host smart-b9a9af21-c5b8-45e5-bc59-5d6233636871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209267064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4209267064
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3970005578
Short name T738
Test name
Test status
Simulation time 1122986109 ps
CPU time 3.87 seconds
Started Apr 23 02:45:01 PM PDT 24
Finished Apr 23 02:45:06 PM PDT 24
Peak memory 215272 kb
Host smart-1a1066a6-adb2-421d-935f-260398e6df83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970005578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3970005578
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2926792024
Short name T789
Test name
Test status
Simulation time 152870018 ps
CPU time 2.03 seconds
Started Apr 23 02:44:57 PM PDT 24
Finished Apr 23 02:45:00 PM PDT 24
Peak memory 216360 kb
Host smart-aa294a7c-4229-40bb-bdd1-2e8dd74c665c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926792024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2926792024
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.751814242
Short name T783
Test name
Test status
Simulation time 647348261 ps
CPU time 14.94 seconds
Started Apr 23 02:45:01 PM PDT 24
Finished Apr 23 02:45:17 PM PDT 24
Peak memory 218868 kb
Host smart-b6889881-9d3d-4b87-b57c-b416e549d924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751814242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.751814242
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4270041645
Short name T128
Test name
Test status
Simulation time 45699429 ps
CPU time 3.32 seconds
Started Apr 23 02:45:00 PM PDT 24
Finished Apr 23 02:45:04 PM PDT 24
Peak memory 216764 kb
Host smart-3757dd1d-8ee0-4ff2-9941-8d63d4643820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270041645 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4270041645
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1460089336
Short name T152
Test name
Test status
Simulation time 663080041 ps
CPU time 2.82 seconds
Started Apr 23 02:45:04 PM PDT 24
Finished Apr 23 02:45:07 PM PDT 24
Peak memory 207048 kb
Host smart-14f96b6a-b364-42f2-84f5-7efbbb888732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460089336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1460089336
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2673300024
Short name T777
Test name
Test status
Simulation time 51961540 ps
CPU time 0.74 seconds
Started Apr 23 02:45:00 PM PDT 24
Finished Apr 23 02:45:02 PM PDT 24
Peak memory 203852 kb
Host smart-27bb61bb-99bc-4028-89ce-fa8c7dd2d58f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673300024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2673300024
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2444890024
Short name T168
Test name
Test status
Simulation time 792242576 ps
CPU time 4.18 seconds
Started Apr 23 02:45:00 PM PDT 24
Finished Apr 23 02:45:04 PM PDT 24
Peak memory 215156 kb
Host smart-d03bb0bf-a926-45f7-a567-caafb8fcb23e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444890024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2444890024
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.694120652
Short name T775
Test name
Test status
Simulation time 125718850 ps
CPU time 3.62 seconds
Started Apr 23 02:45:01 PM PDT 24
Finished Apr 23 02:45:05 PM PDT 24
Peak memory 215388 kb
Host smart-af507564-2893-494f-9f08-0689219ccad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694120652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.694120652
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1449116885
Short name T373
Test name
Test status
Simulation time 216147713 ps
CPU time 6.44 seconds
Started Apr 23 02:45:00 PM PDT 24
Finished Apr 23 02:45:07 PM PDT 24
Peak memory 215252 kb
Host smart-91081972-b00f-4c86-a6af-e49b03a94db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449116885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1449116885
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2464775534
Short name T136
Test name
Test status
Simulation time 146297619 ps
CPU time 2.65 seconds
Started Apr 23 02:45:04 PM PDT 24
Finished Apr 23 02:45:07 PM PDT 24
Peak memory 216304 kb
Host smart-ebeb04bf-ff14-40c7-94a8-ae65202afd17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464775534 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2464775534
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.775071885
Short name T730
Test name
Test status
Simulation time 66739447 ps
CPU time 2.08 seconds
Started Apr 23 02:45:05 PM PDT 24
Finished Apr 23 02:45:07 PM PDT 24
Peak memory 206996 kb
Host smart-b9af6108-fa11-4c24-be98-4f3d881e442a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775071885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.775071885
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.952362261
Short name T724
Test name
Test status
Simulation time 34120203 ps
CPU time 0.72 seconds
Started Apr 23 02:45:03 PM PDT 24
Finished Apr 23 02:45:04 PM PDT 24
Peak memory 203884 kb
Host smart-5578760c-a2e6-4460-a8db-5d2aece6d2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952362261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.952362261
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1421755663
Short name T154
Test name
Test status
Simulation time 191184473 ps
CPU time 1.88 seconds
Started Apr 23 02:45:03 PM PDT 24
Finished Apr 23 02:45:06 PM PDT 24
Peak memory 215140 kb
Host smart-534d8059-3883-4682-bb33-4ead7ff3634c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421755663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1421755663
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1798953030
Short name T774
Test name
Test status
Simulation time 159362253 ps
CPU time 2.4 seconds
Started Apr 23 02:45:03 PM PDT 24
Finished Apr 23 02:45:06 PM PDT 24
Peak memory 215392 kb
Host smart-5afabc10-e1dc-4602-ba7a-5cac628e1e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798953030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1798953030
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3164451592
Short name T822
Test name
Test status
Simulation time 798935493 ps
CPU time 23.26 seconds
Started Apr 23 02:45:03 PM PDT 24
Finished Apr 23 02:45:26 PM PDT 24
Peak memory 216116 kb
Host smart-113a93c3-c135-4cb5-bd89-04f16277d544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164451592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3164451592
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4088147712
Short name T167
Test name
Test status
Simulation time 53812813 ps
CPU time 1.8 seconds
Started Apr 23 02:45:07 PM PDT 24
Finished Apr 23 02:45:09 PM PDT 24
Peak memory 215376 kb
Host smart-487e678a-fc8e-4f01-b7be-2ea36a254956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088147712 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4088147712
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3452328695
Short name T150
Test name
Test status
Simulation time 537375178 ps
CPU time 2.75 seconds
Started Apr 23 02:45:06 PM PDT 24
Finished Apr 23 02:45:09 PM PDT 24
Peak memory 215196 kb
Host smart-10c8beb2-c57d-411b-9e89-9f3651d031d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452328695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3452328695
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3431928572
Short name T810
Test name
Test status
Simulation time 19982383 ps
CPU time 0.73 seconds
Started Apr 23 02:45:04 PM PDT 24
Finished Apr 23 02:45:05 PM PDT 24
Peak memory 203888 kb
Host smart-bae3bb8d-b2a1-4ce3-a48d-ccb8303b2a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431928572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3431928572
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.162659432
Short name T803
Test name
Test status
Simulation time 162522875 ps
CPU time 4.4 seconds
Started Apr 23 02:45:06 PM PDT 24
Finished Apr 23 02:45:11 PM PDT 24
Peak memory 215268 kb
Host smart-6977870c-4615-440c-8e14-ea5ea9a97efc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162659432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.162659432
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1181766796
Short name T33
Test name
Test status
Simulation time 580092677 ps
CPU time 18.61 seconds
Started Apr 23 02:45:03 PM PDT 24
Finished Apr 23 02:45:22 PM PDT 24
Peak memory 215244 kb
Host smart-0ffc2baf-f2fd-4379-90ae-2347725fabb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181766796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1181766796
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3335417295
Short name T110
Test name
Test status
Simulation time 177104184 ps
CPU time 2.64 seconds
Started Apr 23 02:45:10 PM PDT 24
Finished Apr 23 02:45:13 PM PDT 24
Peak memory 217900 kb
Host smart-5537b60c-0b58-4d78-982d-a950ce0e25c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335417295 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3335417295
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1072872438
Short name T164
Test name
Test status
Simulation time 141164036 ps
CPU time 1.94 seconds
Started Apr 23 02:45:11 PM PDT 24
Finished Apr 23 02:45:13 PM PDT 24
Peak memory 207000 kb
Host smart-26830a2b-2c75-49a7-b5c6-92d441341660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072872438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1072872438
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1977417984
Short name T760
Test name
Test status
Simulation time 15473502 ps
CPU time 0.74 seconds
Started Apr 23 02:45:11 PM PDT 24
Finished Apr 23 02:45:12 PM PDT 24
Peak memory 203856 kb
Host smart-05f1faad-e570-4dad-9928-7a7cb985496c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977417984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1977417984
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.439710904
Short name T166
Test name
Test status
Simulation time 502134984 ps
CPU time 2.92 seconds
Started Apr 23 02:45:09 PM PDT 24
Finished Apr 23 02:45:12 PM PDT 24
Peak memory 215168 kb
Host smart-1eada17b-4c21-4921-b093-0415767541c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439710904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.439710904
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3572407883
Short name T118
Test name
Test status
Simulation time 292837797 ps
CPU time 4.07 seconds
Started Apr 23 02:45:08 PM PDT 24
Finished Apr 23 02:45:12 PM PDT 24
Peak memory 215404 kb
Host smart-387df1bf-8343-47c0-b876-3024b9021674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572407883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3572407883
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1887721231
Short name T133
Test name
Test status
Simulation time 208147387 ps
CPU time 6.33 seconds
Started Apr 23 02:45:15 PM PDT 24
Finished Apr 23 02:45:22 PM PDT 24
Peak memory 215216 kb
Host smart-73662070-4ee2-4db2-92ae-0eb96bea1473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887721231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1887721231
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.469674138
Short name T788
Test name
Test status
Simulation time 55317091 ps
CPU time 3.52 seconds
Started Apr 23 02:45:09 PM PDT 24
Finished Apr 23 02:45:13 PM PDT 24
Peak memory 218816 kb
Host smart-0763812a-01ad-4e30-916e-f7196d26d7c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469674138 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.469674138
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4251496727
Short name T771
Test name
Test status
Simulation time 141030529 ps
CPU time 2.56 seconds
Started Apr 23 02:45:09 PM PDT 24
Finished Apr 23 02:45:12 PM PDT 24
Peak memory 215252 kb
Host smart-0cf3ed66-0e23-4ca2-a6dc-0fbd3922f4eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251496727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4251496727
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3746845000
Short name T739
Test name
Test status
Simulation time 51380650 ps
CPU time 0.68 seconds
Started Apr 23 02:45:10 PM PDT 24
Finished Apr 23 02:45:11 PM PDT 24
Peak memory 203560 kb
Host smart-841a033c-aed4-4e9e-9f1b-4dee25b1d129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746845000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3746845000
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2579343182
Short name T827
Test name
Test status
Simulation time 189183424 ps
CPU time 4.09 seconds
Started Apr 23 02:45:10 PM PDT 24
Finished Apr 23 02:45:14 PM PDT 24
Peak memory 215176 kb
Host smart-a521fe13-81d2-4fe5-bf54-e341f755cbda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579343182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2579343182
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3473149550
Short name T800
Test name
Test status
Simulation time 228961705 ps
CPU time 3.55 seconds
Started Apr 23 02:45:10 PM PDT 24
Finished Apr 23 02:45:14 PM PDT 24
Peak memory 215416 kb
Host smart-9b34008e-6d4c-476d-ab0b-0a1dcc735275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473149550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3473149550
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2335846375
Short name T820
Test name
Test status
Simulation time 115552661 ps
CPU time 3.7 seconds
Started Apr 23 02:45:13 PM PDT 24
Finished Apr 23 02:45:17 PM PDT 24
Peak memory 216428 kb
Host smart-9383b017-def4-494f-bdde-13c30eb0fdc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335846375 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2335846375
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3807143834
Short name T148
Test name
Test status
Simulation time 242007208 ps
CPU time 1.87 seconds
Started Apr 23 02:45:15 PM PDT 24
Finished Apr 23 02:45:17 PM PDT 24
Peak memory 215208 kb
Host smart-87be2f22-b410-4c8c-bda3-4aa538467d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807143834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3807143834
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1497030733
Short name T782
Test name
Test status
Simulation time 44116939 ps
CPU time 0.72 seconds
Started Apr 23 02:45:12 PM PDT 24
Finished Apr 23 02:45:14 PM PDT 24
Peak memory 203560 kb
Host smart-58173bc2-17fd-4e41-9ff8-e9cb6dcbcd33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497030733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1497030733
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1616852719
Short name T36
Test name
Test status
Simulation time 180407378 ps
CPU time 2.95 seconds
Started Apr 23 02:45:13 PM PDT 24
Finished Apr 23 02:45:16 PM PDT 24
Peak memory 215236 kb
Host smart-70d28327-9082-4b76-9128-976c168f2172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616852719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1616852719
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3059031117
Short name T757
Test name
Test status
Simulation time 131101869 ps
CPU time 3.74 seconds
Started Apr 23 02:45:11 PM PDT 24
Finished Apr 23 02:45:15 PM PDT 24
Peak memory 215412 kb
Host smart-97663422-a381-4acc-a1d1-b0f1a539e38b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059031117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3059031117
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1325882763
Short name T372
Test name
Test status
Simulation time 718469875 ps
CPU time 15.83 seconds
Started Apr 23 02:45:11 PM PDT 24
Finished Apr 23 02:45:27 PM PDT 24
Peak memory 215848 kb
Host smart-bf38b7e6-423c-4e9f-80bc-593458f74e81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325882763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1325882763
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.582371602
Short name T816
Test name
Test status
Simulation time 185577725 ps
CPU time 2.64 seconds
Started Apr 23 02:45:16 PM PDT 24
Finished Apr 23 02:45:19 PM PDT 24
Peak memory 216568 kb
Host smart-e416bceb-8050-41c0-a689-347e7e374829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582371602 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.582371602
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3616774543
Short name T142
Test name
Test status
Simulation time 272390687 ps
CPU time 2.6 seconds
Started Apr 23 02:45:16 PM PDT 24
Finished Apr 23 02:45:19 PM PDT 24
Peak memory 215168 kb
Host smart-3d643543-fa4a-4d95-8aed-23d01ab72b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616774543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3616774543
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3256120152
Short name T813
Test name
Test status
Simulation time 60989560 ps
CPU time 0.76 seconds
Started Apr 23 02:45:20 PM PDT 24
Finished Apr 23 02:45:21 PM PDT 24
Peak memory 203584 kb
Host smart-021b5bc3-7b2c-4e63-b4d8-0bc731c19798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256120152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3256120152
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3418360982
Short name T799
Test name
Test status
Simulation time 60687055 ps
CPU time 1.9 seconds
Started Apr 23 02:45:18 PM PDT 24
Finished Apr 23 02:45:20 PM PDT 24
Peak memory 215224 kb
Host smart-0967951c-e600-4d5f-ada6-0dbfc46a70a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418360982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3418360982
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.268345091
Short name T754
Test name
Test status
Simulation time 79877639 ps
CPU time 2.09 seconds
Started Apr 23 02:45:15 PM PDT 24
Finished Apr 23 02:45:17 PM PDT 24
Peak memory 215476 kb
Host smart-36a62e82-9de5-4aff-aa8c-80d28efd5e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268345091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.268345091
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4048519214
Short name T371
Test name
Test status
Simulation time 550641308 ps
CPU time 6.92 seconds
Started Apr 23 02:45:13 PM PDT 24
Finished Apr 23 02:45:20 PM PDT 24
Peak memory 215240 kb
Host smart-53448948-2ca7-40bf-97f9-1b770b12b485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048519214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4048519214
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1877346909
Short name T814
Test name
Test status
Simulation time 605692246 ps
CPU time 8.45 seconds
Started Apr 23 02:44:23 PM PDT 24
Finished Apr 23 02:44:32 PM PDT 24
Peak memory 207032 kb
Host smart-0d32c716-9840-4e71-baa3-55d7541f8940
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877346909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1877346909
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3091861
Short name T761
Test name
Test status
Simulation time 5037408024 ps
CPU time 25.08 seconds
Started Apr 23 02:44:27 PM PDT 24
Finished Apr 23 02:44:53 PM PDT 24
Peak memory 207120 kb
Host smart-acbc2762-ecc8-4289-b7e3-385c3fcb9194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_b
it_bash.3091861
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1755296696
Short name T92
Test name
Test status
Simulation time 121316370 ps
CPU time 1.26 seconds
Started Apr 23 02:44:24 PM PDT 24
Finished Apr 23 02:44:26 PM PDT 24
Peak memory 207092 kb
Host smart-f8808100-dd17-4989-9595-01a0ead72d1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755296696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1755296696
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3792184130
Short name T126
Test name
Test status
Simulation time 56231027 ps
CPU time 3.69 seconds
Started Apr 23 02:44:27 PM PDT 24
Finished Apr 23 02:44:31 PM PDT 24
Peak memory 216600 kb
Host smart-095ead36-2c9e-45b0-902f-ef9f8e68df33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792184130 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3792184130
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3346422003
Short name T826
Test name
Test status
Simulation time 58573834 ps
CPU time 1.88 seconds
Started Apr 23 02:44:29 PM PDT 24
Finished Apr 23 02:44:31 PM PDT 24
Peak memory 207008 kb
Host smart-f120f63f-7044-4864-9207-e11c4424a065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346422003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
346422003
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4049878817
Short name T801
Test name
Test status
Simulation time 14771049 ps
CPU time 0.67 seconds
Started Apr 23 02:44:24 PM PDT 24
Finished Apr 23 02:44:25 PM PDT 24
Peak memory 203560 kb
Host smart-48c61e6e-86d8-4e53-95a5-49185ee27d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049878817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
049878817
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2569125322
Short name T824
Test name
Test status
Simulation time 189336241 ps
CPU time 1.24 seconds
Started Apr 23 02:44:24 PM PDT 24
Finished Apr 23 02:44:25 PM PDT 24
Peak memory 215332 kb
Host smart-a40030a6-b80a-4a40-9721-4ba490fc77f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569125322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2569125322
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2736256295
Short name T729
Test name
Test status
Simulation time 11208423 ps
CPU time 0.67 seconds
Started Apr 23 02:44:25 PM PDT 24
Finished Apr 23 02:44:26 PM PDT 24
Peak memory 203472 kb
Host smart-91c60beb-301a-4820-b5a5-1936648e18c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736256295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2736256295
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1653320898
Short name T155
Test name
Test status
Simulation time 57535595 ps
CPU time 1.77 seconds
Started Apr 23 02:44:26 PM PDT 24
Finished Apr 23 02:44:28 PM PDT 24
Peak memory 206996 kb
Host smart-33695d35-c8cb-4365-94fa-2e84c21ffb8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653320898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1653320898
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1617579705
Short name T798
Test name
Test status
Simulation time 179277615 ps
CPU time 1.28 seconds
Started Apr 23 02:44:21 PM PDT 24
Finished Apr 23 02:44:22 PM PDT 24
Peak memory 216460 kb
Host smart-990d0dfb-70b3-4754-a1bc-13977c58fb33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617579705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
617579705
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1857232091
Short name T765
Test name
Test status
Simulation time 3212392483 ps
CPU time 14.25 seconds
Started Apr 23 02:44:21 PM PDT 24
Finished Apr 23 02:44:35 PM PDT 24
Peak memory 215440 kb
Host smart-c8dedb59-0d80-46f4-b70f-bfc11b9cd990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857232091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1857232091
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2204861049
Short name T796
Test name
Test status
Simulation time 32737162 ps
CPU time 0.68 seconds
Started Apr 23 02:45:18 PM PDT 24
Finished Apr 23 02:45:19 PM PDT 24
Peak memory 203868 kb
Host smart-dc5f68a3-c43b-45ba-84f3-d99932d687d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204861049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2204861049
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1155060698
Short name T750
Test name
Test status
Simulation time 21599047 ps
CPU time 0.68 seconds
Started Apr 23 02:45:17 PM PDT 24
Finished Apr 23 02:45:18 PM PDT 24
Peak memory 203852 kb
Host smart-f6873507-068a-4eb5-8215-dd5408fad316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155060698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1155060698
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3156373366
Short name T172
Test name
Test status
Simulation time 49938236 ps
CPU time 0.8 seconds
Started Apr 23 02:45:17 PM PDT 24
Finished Apr 23 02:45:19 PM PDT 24
Peak memory 203600 kb
Host smart-0b40d14c-d913-4bab-8dc1-2b46704a1bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156373366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3156373366
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3448921779
Short name T723
Test name
Test status
Simulation time 56577234 ps
CPU time 0.71 seconds
Started Apr 23 02:45:18 PM PDT 24
Finished Apr 23 02:45:19 PM PDT 24
Peak memory 203568 kb
Host smart-d65ea4e2-d8cd-42d2-9939-088a42f1320d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448921779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3448921779
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1234717561
Short name T744
Test name
Test status
Simulation time 62054625 ps
CPU time 0.73 seconds
Started Apr 23 02:45:17 PM PDT 24
Finished Apr 23 02:45:18 PM PDT 24
Peak memory 203560 kb
Host smart-b86048f9-ca43-433c-8f56-4e5344880923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234717561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1234717561
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1823776022
Short name T737
Test name
Test status
Simulation time 15585625 ps
CPU time 0.7 seconds
Started Apr 23 02:45:18 PM PDT 24
Finished Apr 23 02:45:19 PM PDT 24
Peak memory 203624 kb
Host smart-a58eae55-9c03-414d-a406-0c4007ef4970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823776022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1823776022
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4106872443
Short name T726
Test name
Test status
Simulation time 29693410 ps
CPU time 0.7 seconds
Started Apr 23 02:45:19 PM PDT 24
Finished Apr 23 02:45:20 PM PDT 24
Peak memory 203592 kb
Host smart-a133cb6c-741d-4681-bb13-3a4818436ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106872443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4106872443
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2564530146
Short name T170
Test name
Test status
Simulation time 47594196 ps
CPU time 0.73 seconds
Started Apr 23 02:45:20 PM PDT 24
Finished Apr 23 02:45:21 PM PDT 24
Peak memory 203584 kb
Host smart-168542f8-801b-4b0a-9da7-5e1d82df274f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564530146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2564530146
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1106669787
Short name T746
Test name
Test status
Simulation time 11745454 ps
CPU time 0.76 seconds
Started Apr 23 02:45:19 PM PDT 24
Finished Apr 23 02:45:21 PM PDT 24
Peak memory 203596 kb
Host smart-0bc1b697-5b59-440c-ab3c-2c6d4ac9a5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106669787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1106669787
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3205946513
Short name T785
Test name
Test status
Simulation time 43295817 ps
CPU time 0.74 seconds
Started Apr 23 02:45:20 PM PDT 24
Finished Apr 23 02:45:21 PM PDT 24
Peak memory 203608 kb
Host smart-14c3aabf-d2a1-4a15-a939-4f2ef38b3bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205946513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3205946513
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.102204046
Short name T758
Test name
Test status
Simulation time 1567983450 ps
CPU time 8.54 seconds
Started Apr 23 02:44:35 PM PDT 24
Finished Apr 23 02:44:45 PM PDT 24
Peak memory 207036 kb
Host smart-969b3939-fa72-47d8-be39-49ea202dff28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102204046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.102204046
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1309361116
Short name T149
Test name
Test status
Simulation time 15643239912 ps
CPU time 12.88 seconds
Started Apr 23 02:44:34 PM PDT 24
Finished Apr 23 02:44:47 PM PDT 24
Peak memory 207064 kb
Host smart-ed7250c2-841b-45a7-af2f-60411bfcdbb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309361116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1309361116
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3626202302
Short name T745
Test name
Test status
Simulation time 148821816 ps
CPU time 1.39 seconds
Started Apr 23 02:44:31 PM PDT 24
Finished Apr 23 02:44:33 PM PDT 24
Peak memory 216212 kb
Host smart-088bc41f-b8af-4b28-bb20-020fda417458
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626202302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3626202302
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1204061727
Short name T770
Test name
Test status
Simulation time 46610670 ps
CPU time 1.71 seconds
Started Apr 23 02:44:33 PM PDT 24
Finished Apr 23 02:44:36 PM PDT 24
Peak memory 215432 kb
Host smart-f29ce5c9-559e-4e59-afd9-128b886ba14f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204061727 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1204061727
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1602507321
Short name T811
Test name
Test status
Simulation time 122558521 ps
CPU time 1.9 seconds
Started Apr 23 02:44:29 PM PDT 24
Finished Apr 23 02:44:31 PM PDT 24
Peak memory 215228 kb
Host smart-3d0d0419-7231-4cc4-80bd-1920c092af9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602507321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
602507321
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1476692575
Short name T727
Test name
Test status
Simulation time 31016407 ps
CPU time 0.75 seconds
Started Apr 23 02:44:27 PM PDT 24
Finished Apr 23 02:44:28 PM PDT 24
Peak memory 203804 kb
Host smart-56305738-fc75-4557-9575-ae558ba114cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476692575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
476692575
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1754111528
Short name T791
Test name
Test status
Simulation time 47527955 ps
CPU time 1.22 seconds
Started Apr 23 02:44:31 PM PDT 24
Finished Apr 23 02:44:32 PM PDT 24
Peak memory 215340 kb
Host smart-2a4f8c74-f28a-4918-8bee-b72b49cea89b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754111528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1754111528
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2561141142
Short name T732
Test name
Test status
Simulation time 74688692 ps
CPU time 0.64 seconds
Started Apr 23 02:44:31 PM PDT 24
Finished Apr 23 02:44:32 PM PDT 24
Peak memory 203536 kb
Host smart-eb2bf7ba-5804-4d15-aa58-6e6d15949b73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561141142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2561141142
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1543278583
Short name T823
Test name
Test status
Simulation time 296238989 ps
CPU time 3.72 seconds
Started Apr 23 02:44:34 PM PDT 24
Finished Apr 23 02:44:38 PM PDT 24
Peak memory 215252 kb
Host smart-c2bc581b-9550-4678-b81d-16263dff2356
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543278583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1543278583
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2236028525
Short name T787
Test name
Test status
Simulation time 792509054 ps
CPU time 4.73 seconds
Started Apr 23 02:44:27 PM PDT 24
Finished Apr 23 02:44:32 PM PDT 24
Peak memory 215388 kb
Host smart-96fea2a4-b1e9-4829-99af-a3c674f21263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236028525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
236028525
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.626891334
Short name T132
Test name
Test status
Simulation time 1899723096 ps
CPU time 18.59 seconds
Started Apr 23 02:44:27 PM PDT 24
Finished Apr 23 02:44:46 PM PDT 24
Peak memory 215236 kb
Host smart-7933cf20-b426-4208-83e4-da37ae08cc87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626891334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.626891334
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2997629156
Short name T809
Test name
Test status
Simulation time 19885020 ps
CPU time 0.74 seconds
Started Apr 23 02:45:20 PM PDT 24
Finished Apr 23 02:45:21 PM PDT 24
Peak memory 203844 kb
Host smart-1e77169e-e560-4027-a1de-dd3d1e608257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997629156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2997629156
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.850898567
Short name T734
Test name
Test status
Simulation time 12011933 ps
CPU time 0.71 seconds
Started Apr 23 02:45:20 PM PDT 24
Finished Apr 23 02:45:21 PM PDT 24
Peak memory 203612 kb
Host smart-0486e2ba-3581-4aae-96dc-d7317957257a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850898567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.850898567
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1167680750
Short name T797
Test name
Test status
Simulation time 25058493 ps
CPU time 0.77 seconds
Started Apr 23 02:45:20 PM PDT 24
Finished Apr 23 02:45:21 PM PDT 24
Peak memory 203872 kb
Host smart-f57f7fc5-5996-466e-a019-928371421c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167680750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1167680750
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.826664700
Short name T740
Test name
Test status
Simulation time 48452646 ps
CPU time 0.72 seconds
Started Apr 23 02:45:19 PM PDT 24
Finished Apr 23 02:45:20 PM PDT 24
Peak memory 203576 kb
Host smart-5fc97afb-fa6f-4581-90db-927c6b190ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826664700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.826664700
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.727704544
Short name T722
Test name
Test status
Simulation time 50415539 ps
CPU time 0.73 seconds
Started Apr 23 02:45:23 PM PDT 24
Finished Apr 23 02:45:24 PM PDT 24
Peak memory 203864 kb
Host smart-0e2e79ae-1344-4092-b65e-79c284aa790d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727704544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.727704544
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.261348757
Short name T807
Test name
Test status
Simulation time 17240685 ps
CPU time 0.79 seconds
Started Apr 23 02:45:22 PM PDT 24
Finished Apr 23 02:45:23 PM PDT 24
Peak memory 203656 kb
Host smart-edc303c2-6dc8-4a5d-9aec-8d72aa8203a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261348757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.261348757
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3828462974
Short name T763
Test name
Test status
Simulation time 38477696 ps
CPU time 0.71 seconds
Started Apr 23 02:45:22 PM PDT 24
Finished Apr 23 02:45:23 PM PDT 24
Peak memory 203868 kb
Host smart-0438255f-f1a6-4f05-a96c-253d1efc5424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828462974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3828462974
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1323503491
Short name T171
Test name
Test status
Simulation time 18049844 ps
CPU time 0.74 seconds
Started Apr 23 02:45:22 PM PDT 24
Finished Apr 23 02:45:23 PM PDT 24
Peak memory 203604 kb
Host smart-b42f77d4-025a-490c-bcc9-891d1bdfe0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323503491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1323503491
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2673035193
Short name T825
Test name
Test status
Simulation time 43559488 ps
CPU time 0.7 seconds
Started Apr 23 02:45:22 PM PDT 24
Finished Apr 23 02:45:23 PM PDT 24
Peak memory 203588 kb
Host smart-7228ae09-c283-43b3-94b3-519358468bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673035193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2673035193
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.175512920
Short name T733
Test name
Test status
Simulation time 12881897 ps
CPU time 0.7 seconds
Started Apr 23 02:45:23 PM PDT 24
Finished Apr 23 02:45:24 PM PDT 24
Peak memory 203544 kb
Host smart-c8955c4c-9443-4700-a61d-878cbbf65894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175512920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.175512920
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.963105415
Short name T802
Test name
Test status
Simulation time 1528898150 ps
CPU time 8.16 seconds
Started Apr 23 02:44:40 PM PDT 24
Finished Apr 23 02:44:49 PM PDT 24
Peak memory 207032 kb
Host smart-9dbd6145-be92-4d0b-a232-b092489afea7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963105415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.963105415
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.188863862
Short name T165
Test name
Test status
Simulation time 2245294883 ps
CPU time 13.74 seconds
Started Apr 23 02:44:43 PM PDT 24
Finished Apr 23 02:44:57 PM PDT 24
Peak memory 207088 kb
Host smart-cfc53433-0235-4a88-8fbc-99fec36c8c24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188863862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.188863862
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3025223953
Short name T93
Test name
Test status
Simulation time 78976269 ps
CPU time 1.39 seconds
Started Apr 23 02:44:37 PM PDT 24
Finished Apr 23 02:44:39 PM PDT 24
Peak memory 206980 kb
Host smart-25d3cb0e-920c-4395-aa15-0596f0b54f82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025223953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3025223953
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1519121963
Short name T112
Test name
Test status
Simulation time 57195546 ps
CPU time 1.85 seconds
Started Apr 23 02:44:44 PM PDT 24
Finished Apr 23 02:44:46 PM PDT 24
Peak memory 215384 kb
Host smart-04bdb8b7-b0c6-463c-ae0e-91a7e6533954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519121963 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1519121963
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.505235225
Short name T819
Test name
Test status
Simulation time 29678671 ps
CPU time 1.9 seconds
Started Apr 23 02:44:40 PM PDT 24
Finished Apr 23 02:44:43 PM PDT 24
Peak memory 215244 kb
Host smart-8212b7ec-9658-447a-a405-f9b3a5e9594a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505235225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.505235225
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4194390876
Short name T749
Test name
Test status
Simulation time 31848082 ps
CPU time 0.76 seconds
Started Apr 23 02:44:33 PM PDT 24
Finished Apr 23 02:44:35 PM PDT 24
Peak memory 203612 kb
Host smart-32cfe92e-f07d-44a6-bb74-a39e190d6906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194390876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
194390876
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3031610771
Short name T143
Test name
Test status
Simulation time 49318145 ps
CPU time 1.77 seconds
Started Apr 23 02:44:37 PM PDT 24
Finished Apr 23 02:44:39 PM PDT 24
Peak memory 215368 kb
Host smart-d5dbbd20-86e4-47ba-a71b-0baebfc854d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031610771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3031610771
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2456000838
Short name T736
Test name
Test status
Simulation time 25205022 ps
CPU time 0.64 seconds
Started Apr 23 02:44:36 PM PDT 24
Finished Apr 23 02:44:38 PM PDT 24
Peak memory 203868 kb
Host smart-f607a571-038c-42de-804c-c0aed8c77a02
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456000838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2456000838
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.638851539
Short name T747
Test name
Test status
Simulation time 112397279 ps
CPU time 2.83 seconds
Started Apr 23 02:44:42 PM PDT 24
Finished Apr 23 02:44:45 PM PDT 24
Peak memory 215232 kb
Host smart-ac11fe7c-d500-46d7-b4eb-e276d8e7e442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638851539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.638851539
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3122539889
Short name T116
Test name
Test status
Simulation time 746424450 ps
CPU time 3.92 seconds
Started Apr 23 02:44:34 PM PDT 24
Finished Apr 23 02:44:38 PM PDT 24
Peak memory 215356 kb
Host smart-ab29490c-4724-4dc0-94f5-93af19809702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122539889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
122539889
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3782041108
Short name T368
Test name
Test status
Simulation time 780994158 ps
CPU time 11.97 seconds
Started Apr 23 02:44:33 PM PDT 24
Finished Apr 23 02:44:46 PM PDT 24
Peak memory 215280 kb
Host smart-b1ddcee8-5232-46e9-b800-7682ebfaac36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782041108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3782041108
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1144675019
Short name T778
Test name
Test status
Simulation time 50307264 ps
CPU time 0.73 seconds
Started Apr 23 02:45:25 PM PDT 24
Finished Apr 23 02:45:26 PM PDT 24
Peak memory 203592 kb
Host smart-76989dd8-a602-409b-b2c0-5d9a00c800de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144675019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1144675019
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2024518104
Short name T772
Test name
Test status
Simulation time 35721096 ps
CPU time 0.67 seconds
Started Apr 23 02:45:23 PM PDT 24
Finished Apr 23 02:45:24 PM PDT 24
Peak memory 203596 kb
Host smart-ecdf242d-a198-4b9a-9fbe-b26cbefbc949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024518104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2024518104
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1239822784
Short name T720
Test name
Test status
Simulation time 15965529 ps
CPU time 0.72 seconds
Started Apr 23 02:45:23 PM PDT 24
Finished Apr 23 02:45:24 PM PDT 24
Peak memory 203872 kb
Host smart-f446f7cd-ae8d-4284-b99b-f13518d2e1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239822784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1239822784
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1942836095
Short name T815
Test name
Test status
Simulation time 14019732 ps
CPU time 0.68 seconds
Started Apr 23 02:45:22 PM PDT 24
Finished Apr 23 02:45:23 PM PDT 24
Peak memory 203528 kb
Host smart-c2b26053-696f-4db9-b8e8-5844d2e6c15b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942836095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1942836095
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2064205933
Short name T725
Test name
Test status
Simulation time 48773928 ps
CPU time 0.68 seconds
Started Apr 23 02:45:23 PM PDT 24
Finished Apr 23 02:45:24 PM PDT 24
Peak memory 203568 kb
Host smart-0252ba6b-8bab-402a-bddf-7e4d4b85e1c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064205933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2064205933
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3745524148
Short name T768
Test name
Test status
Simulation time 20775450 ps
CPU time 0.71 seconds
Started Apr 23 02:45:22 PM PDT 24
Finished Apr 23 02:45:23 PM PDT 24
Peak memory 203904 kb
Host smart-7d1b221e-0214-4313-b7a6-45b4dc19684e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745524148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3745524148
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2797457652
Short name T762
Test name
Test status
Simulation time 13141672 ps
CPU time 0.7 seconds
Started Apr 23 02:45:26 PM PDT 24
Finished Apr 23 02:45:27 PM PDT 24
Peak memory 203568 kb
Host smart-af940688-dba1-46b9-8e1f-7b92557ef356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797457652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2797457652
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.891840510
Short name T752
Test name
Test status
Simulation time 14123596 ps
CPU time 0.7 seconds
Started Apr 23 02:45:27 PM PDT 24
Finished Apr 23 02:45:28 PM PDT 24
Peak memory 203884 kb
Host smart-ae834b66-f10e-49c1-b729-c9a06e290895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891840510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.891840510
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2823765935
Short name T766
Test name
Test status
Simulation time 35316447 ps
CPU time 0.7 seconds
Started Apr 23 02:45:26 PM PDT 24
Finished Apr 23 02:45:27 PM PDT 24
Peak memory 203628 kb
Host smart-bb7836d8-9f86-45ff-9cb0-ff0efd9e2332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823765935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2823765935
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2527490015
Short name T759
Test name
Test status
Simulation time 16324534 ps
CPU time 0.71 seconds
Started Apr 23 02:45:27 PM PDT 24
Finished Apr 23 02:45:28 PM PDT 24
Peak memory 203900 kb
Host smart-44c3494d-811b-4ed6-99d1-a0d472fead03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527490015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2527490015
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2237571573
Short name T129
Test name
Test status
Simulation time 311855857 ps
CPU time 3.68 seconds
Started Apr 23 02:44:45 PM PDT 24
Finished Apr 23 02:44:49 PM PDT 24
Peak memory 218144 kb
Host smart-edd7b3f6-fc6e-463e-8d78-9b5d4da96708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237571573 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2237571573
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.26932994
Short name T163
Test name
Test status
Simulation time 328090018 ps
CPU time 2.2 seconds
Started Apr 23 02:44:44 PM PDT 24
Finished Apr 23 02:44:46 PM PDT 24
Peak memory 215176 kb
Host smart-50c80857-5dde-4e80-ad27-91ff45a97dce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.26932994
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3905014110
Short name T755
Test name
Test status
Simulation time 20724057 ps
CPU time 0.78 seconds
Started Apr 23 02:44:52 PM PDT 24
Finished Apr 23 02:44:53 PM PDT 24
Peak memory 203580 kb
Host smart-53a49c31-554a-4ee0-8cb4-7974c054f71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905014110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
905014110
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2737478392
Short name T127
Test name
Test status
Simulation time 150245384 ps
CPU time 4.25 seconds
Started Apr 23 02:44:42 PM PDT 24
Finished Apr 23 02:44:47 PM PDT 24
Peak memory 215260 kb
Host smart-f6042ce0-9a5a-46e7-b4d7-890db40ab37f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737478392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2737478392
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2024637297
Short name T756
Test name
Test status
Simulation time 230127204 ps
CPU time 3.55 seconds
Started Apr 23 02:44:54 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 216792 kb
Host smart-db9c243d-f0e4-46df-9e80-1b17abf204b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024637297 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2024637297
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2862777620
Short name T753
Test name
Test status
Simulation time 71624878 ps
CPU time 1.9 seconds
Started Apr 23 02:44:46 PM PDT 24
Finished Apr 23 02:44:49 PM PDT 24
Peak memory 215152 kb
Host smart-b9bec9bd-149a-4a2c-91eb-d46f7615520a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862777620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
862777620
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2733797618
Short name T793
Test name
Test status
Simulation time 57501267 ps
CPU time 0.7 seconds
Started Apr 23 02:44:46 PM PDT 24
Finished Apr 23 02:44:47 PM PDT 24
Peak memory 203568 kb
Host smart-dfd71263-a981-42b4-8152-91cd29ef27a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733797618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
733797618
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.659804643
Short name T805
Test name
Test status
Simulation time 527990749 ps
CPU time 2.87 seconds
Started Apr 23 02:44:46 PM PDT 24
Finished Apr 23 02:44:49 PM PDT 24
Peak memory 215288 kb
Host smart-51c5886c-bc8d-4035-b64d-6c386b526a1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659804643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.659804643
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2063357981
Short name T773
Test name
Test status
Simulation time 749476184 ps
CPU time 1.85 seconds
Started Apr 23 02:44:44 PM PDT 24
Finished Apr 23 02:44:47 PM PDT 24
Peak memory 215448 kb
Host smart-b6041658-2ff6-45d5-ba72-d95eecb3a6f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063357981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
063357981
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.901706795
Short name T131
Test name
Test status
Simulation time 3794200123 ps
CPU time 20.69 seconds
Started Apr 23 02:44:45 PM PDT 24
Finished Apr 23 02:45:06 PM PDT 24
Peak memory 215356 kb
Host smart-47ebce5f-37c3-4f9e-b982-a22c6e485f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901706795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.901706795
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1185174324
Short name T786
Test name
Test status
Simulation time 86036156 ps
CPU time 1.62 seconds
Started Apr 23 02:44:51 PM PDT 24
Finished Apr 23 02:44:53 PM PDT 24
Peak memory 215444 kb
Host smart-09995a8a-541a-4683-95e0-7e0aad91c817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185174324 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1185174324
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1764122094
Short name T151
Test name
Test status
Simulation time 103790411 ps
CPU time 2.64 seconds
Started Apr 23 02:44:47 PM PDT 24
Finished Apr 23 02:44:50 PM PDT 24
Peak memory 207048 kb
Host smart-554deda3-25ca-46cc-b1f5-a356dc467b47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764122094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
764122094
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.145063811
Short name T721
Test name
Test status
Simulation time 32868254 ps
CPU time 0.73 seconds
Started Apr 23 02:44:52 PM PDT 24
Finished Apr 23 02:44:53 PM PDT 24
Peak memory 203884 kb
Host smart-b644aac5-9c2a-48d6-b362-603693508c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145063811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.145063811
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2574162596
Short name T156
Test name
Test status
Simulation time 148203929 ps
CPU time 3.81 seconds
Started Apr 23 02:44:46 PM PDT 24
Finished Apr 23 02:44:51 PM PDT 24
Peak memory 215176 kb
Host smart-9096fef4-bb96-4d97-8d33-764ab3fa8ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574162596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2574162596
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3622436495
Short name T125
Test name
Test status
Simulation time 132153819 ps
CPU time 3.44 seconds
Started Apr 23 02:44:47 PM PDT 24
Finished Apr 23 02:44:51 PM PDT 24
Peak memory 215392 kb
Host smart-db352279-8d9c-4a4a-9ddf-3a6324235b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622436495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
622436495
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.135884048
Short name T781
Test name
Test status
Simulation time 9132273886 ps
CPU time 20.72 seconds
Started Apr 23 02:44:47 PM PDT 24
Finished Apr 23 02:45:08 PM PDT 24
Peak memory 215328 kb
Host smart-7dd26f20-58a8-4955-ab4e-b69b09000272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135884048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.135884048
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3398555474
Short name T812
Test name
Test status
Simulation time 54231253 ps
CPU time 1.63 seconds
Started Apr 23 02:44:49 PM PDT 24
Finished Apr 23 02:44:51 PM PDT 24
Peak memory 215304 kb
Host smart-4bb0e3d4-c9c2-45df-8db3-3ad71d914949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398555474 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3398555474
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1319581253
Short name T153
Test name
Test status
Simulation time 69661379 ps
CPU time 1.24 seconds
Started Apr 23 02:44:51 PM PDT 24
Finished Apr 23 02:44:53 PM PDT 24
Peak memory 207076 kb
Host smart-4f49bbdf-f8ad-4fad-a4c3-d80d82dddf91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319581253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
319581253
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.923878041
Short name T741
Test name
Test status
Simulation time 34243755 ps
CPU time 0.67 seconds
Started Apr 23 02:44:51 PM PDT 24
Finished Apr 23 02:44:52 PM PDT 24
Peak memory 203592 kb
Host smart-ed29d1c5-5b2f-43c9-a8ee-f1ea7b7a022d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923878041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.923878041
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.370267916
Short name T37
Test name
Test status
Simulation time 266785219 ps
CPU time 2.86 seconds
Started Apr 23 02:44:51 PM PDT 24
Finished Apr 23 02:44:54 PM PDT 24
Peak memory 215172 kb
Host smart-e0d3d96d-7179-42fa-930e-e56964795ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370267916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.370267916
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1892073423
Short name T130
Test name
Test status
Simulation time 1803307101 ps
CPU time 2.99 seconds
Started Apr 23 02:44:50 PM PDT 24
Finished Apr 23 02:44:54 PM PDT 24
Peak memory 215348 kb
Host smart-d3385b98-b494-4e05-b202-f194fb8b3b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892073423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
892073423
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4027822871
Short name T370
Test name
Test status
Simulation time 397477074 ps
CPU time 7.03 seconds
Started Apr 23 02:44:50 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 215256 kb
Host smart-e719cabe-ca25-477a-bf2f-6db659470b24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027822871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4027822871
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3462948927
Short name T764
Test name
Test status
Simulation time 48017550 ps
CPU time 1.61 seconds
Started Apr 23 02:44:59 PM PDT 24
Finished Apr 23 02:45:01 PM PDT 24
Peak memory 215364 kb
Host smart-3fd34248-135e-4a86-9ac1-498ea18463ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462948927 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3462948927
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1818975673
Short name T147
Test name
Test status
Simulation time 42095371 ps
CPU time 1.29 seconds
Started Apr 23 02:44:53 PM PDT 24
Finished Apr 23 02:44:55 PM PDT 24
Peak memory 207068 kb
Host smart-e4d08515-9e66-436b-9bc9-ba3cf1039b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818975673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
818975673
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3111424184
Short name T821
Test name
Test status
Simulation time 16233652 ps
CPU time 0.74 seconds
Started Apr 23 02:44:55 PM PDT 24
Finished Apr 23 02:44:56 PM PDT 24
Peak memory 203616 kb
Host smart-17e26fae-d06e-4fe4-8552-be7844cccf69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111424184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
111424184
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.285539323
Short name T742
Test name
Test status
Simulation time 469616582 ps
CPU time 4.18 seconds
Started Apr 23 02:44:56 PM PDT 24
Finished Apr 23 02:45:01 PM PDT 24
Peak memory 215244 kb
Host smart-1580fffb-f338-4cd6-ac8f-3bbfddd3f388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285539323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.285539323
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2111214923
Short name T794
Test name
Test status
Simulation time 135985025 ps
CPU time 4.12 seconds
Started Apr 23 02:44:54 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 215448 kb
Host smart-a1f21a06-9d9a-4f9e-8707-7d0ec490fe1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111214923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
111214923
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3159250359
Short name T134
Test name
Test status
Simulation time 726883527 ps
CPU time 8.26 seconds
Started Apr 23 02:44:52 PM PDT 24
Finished Apr 23 02:45:01 PM PDT 24
Peak memory 215220 kb
Host smart-3f23e18d-6207-4905-855d-afa9cb4e9147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159250359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3159250359
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4294187969
Short name T528
Test name
Test status
Simulation time 12015906 ps
CPU time 0.72 seconds
Started Apr 23 03:14:28 PM PDT 24
Finished Apr 23 03:14:30 PM PDT 24
Peak memory 206040 kb
Host smart-bc11e10c-a8d5-4c6f-920e-32fda3badd96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294187969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
294187969
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3329757471
Short name T26
Test name
Test status
Simulation time 1853728927 ps
CPU time 4.11 seconds
Started Apr 23 03:14:17 PM PDT 24
Finished Apr 23 03:14:22 PM PDT 24
Peak memory 219388 kb
Host smart-32c7a533-9b96-421e-9c4d-b42bca4fce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329757471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3329757471
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1264773468
Short name T567
Test name
Test status
Simulation time 43121800 ps
CPU time 0.74 seconds
Started Apr 23 03:13:53 PM PDT 24
Finished Apr 23 03:13:54 PM PDT 24
Peak memory 206452 kb
Host smart-1f4fd5de-dfbd-427d-96a0-436dd7154943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264773468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1264773468
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2633280232
Short name T306
Test name
Test status
Simulation time 5439102251 ps
CPU time 84.81 seconds
Started Apr 23 03:14:20 PM PDT 24
Finished Apr 23 03:15:46 PM PDT 24
Peak memory 233308 kb
Host smart-3d45a96a-d835-4f83-95d2-344ee5045677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633280232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2633280232
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2178143187
Short name T699
Test name
Test status
Simulation time 46788640 ps
CPU time 2.46 seconds
Started Apr 23 03:14:03 PM PDT 24
Finished Apr 23 03:14:06 PM PDT 24
Peak memory 222580 kb
Host smart-daaf2669-70f4-451b-974e-0f8d2575a66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178143187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2178143187
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1277217149
Short name T270
Test name
Test status
Simulation time 3102691793 ps
CPU time 5.12 seconds
Started Apr 23 03:14:04 PM PDT 24
Finished Apr 23 03:14:10 PM PDT 24
Peak memory 219472 kb
Host smart-8a7d99e2-726d-4d84-a71a-4f75f03ea77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277217149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1277217149
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3240313895
Short name T632
Test name
Test status
Simulation time 478050058 ps
CPU time 3.75 seconds
Started Apr 23 03:14:23 PM PDT 24
Finished Apr 23 03:14:28 PM PDT 24
Peak memory 220796 kb
Host smart-2b744b28-dc24-4e46-8c0f-ed85238133e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240313895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3240313895
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1806393517
Short name T50
Test name
Test status
Simulation time 171819642 ps
CPU time 1.27 seconds
Started Apr 23 03:14:28 PM PDT 24
Finished Apr 23 03:14:30 PM PDT 24
Peak memory 235368 kb
Host smart-830d9dd8-eb82-4d1b-a1b1-9a8151b044ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806393517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1806393517
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4188783299
Short name T23
Test name
Test status
Simulation time 42862577 ps
CPU time 0.97 seconds
Started Apr 23 03:14:27 PM PDT 24
Finished Apr 23 03:14:28 PM PDT 24
Peak memory 207256 kb
Host smart-3b9a35c1-59ad-4cc4-a104-59c8945f7cf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188783299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4188783299
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.706189931
Short name T601
Test name
Test status
Simulation time 2889074617 ps
CPU time 3.05 seconds
Started Apr 23 03:13:58 PM PDT 24
Finished Apr 23 03:14:01 PM PDT 24
Peak memory 208492 kb
Host smart-07c3a993-8698-4960-a178-373f801565b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706189931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.706189931
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2531101767
Short name T593
Test name
Test status
Simulation time 31048988 ps
CPU time 1.12 seconds
Started Apr 23 03:14:05 PM PDT 24
Finished Apr 23 03:14:07 PM PDT 24
Peak memory 208112 kb
Host smart-dc951bba-16af-42c4-8157-9bef95a082ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531101767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2531101767
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1178959225
Short name T485
Test name
Test status
Simulation time 298770647 ps
CPU time 1.12 seconds
Started Apr 23 03:14:04 PM PDT 24
Finished Apr 23 03:14:06 PM PDT 24
Peak memory 207356 kb
Host smart-d623b66a-35b6-4599-8b56-992d136ed7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178959225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1178959225
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3109453898
Short name T577
Test name
Test status
Simulation time 30182066 ps
CPU time 0.71 seconds
Started Apr 23 03:14:43 PM PDT 24
Finished Apr 23 03:14:45 PM PDT 24
Peak memory 206116 kb
Host smart-d501b70d-ac80-4070-b2f6-68b83005d45f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109453898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
109453898
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.294620348
Short name T698
Test name
Test status
Simulation time 8754006177 ps
CPU time 12.79 seconds
Started Apr 23 03:14:43 PM PDT 24
Finished Apr 23 03:14:56 PM PDT 24
Peak memory 219552 kb
Host smart-35de1887-b475-4e07-a961-a9353fde11f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294620348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.294620348
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3838823778
Short name T461
Test name
Test status
Simulation time 57705012 ps
CPU time 0.77 seconds
Started Apr 23 03:14:31 PM PDT 24
Finished Apr 23 03:14:33 PM PDT 24
Peak memory 207188 kb
Host smart-8b7b590d-374c-49e5-8cfd-f97a6fb60de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838823778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3838823778
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4103273003
Short name T215
Test name
Test status
Simulation time 729372070 ps
CPU time 9.66 seconds
Started Apr 23 03:14:35 PM PDT 24
Finished Apr 23 03:14:45 PM PDT 24
Peak memory 219540 kb
Host smart-4239a21e-fa39-4262-82c6-3e3457dbade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103273003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4103273003
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2957680751
Short name T254
Test name
Test status
Simulation time 1559106995 ps
CPU time 8.86 seconds
Started Apr 23 03:14:34 PM PDT 24
Finished Apr 23 03:14:43 PM PDT 24
Peak memory 219328 kb
Host smart-7fe684ed-127a-45a0-a517-320e0877a0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957680751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2957680751
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3663501108
Short name T271
Test name
Test status
Simulation time 2822786521 ps
CPU time 3.44 seconds
Started Apr 23 03:14:34 PM PDT 24
Finished Apr 23 03:14:38 PM PDT 24
Peak memory 219340 kb
Host smart-d66bbe4f-62eb-4786-941a-92bc82856c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663501108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3663501108
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3791740673
Short name T4
Test name
Test status
Simulation time 411346670 ps
CPU time 4.03 seconds
Started Apr 23 03:14:45 PM PDT 24
Finished Apr 23 03:14:49 PM PDT 24
Peak memory 219632 kb
Host smart-399ff193-2874-4046-97c1-140f844ade7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3791740673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3791740673
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4088134202
Short name T49
Test name
Test status
Simulation time 463168308 ps
CPU time 1.07 seconds
Started Apr 23 03:14:43 PM PDT 24
Finished Apr 23 03:14:45 PM PDT 24
Peak memory 235320 kb
Host smart-969ade65-4d31-4f6f-951f-f5c3bee28ed0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088134202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4088134202
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2251359517
Short name T675
Test name
Test status
Simulation time 119939854 ps
CPU time 1.02 seconds
Started Apr 23 03:14:44 PM PDT 24
Finished Apr 23 03:14:46 PM PDT 24
Peak memory 207588 kb
Host smart-f8875513-0bcd-4bad-8486-1a546f73ddfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251359517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2251359517
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1392961940
Short name T612
Test name
Test status
Simulation time 1344495564 ps
CPU time 8.24 seconds
Started Apr 23 03:14:30 PM PDT 24
Finished Apr 23 03:14:39 PM PDT 24
Peak memory 216840 kb
Host smart-a8bb6fa2-d19c-428a-bb8a-fa5db182e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392961940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1392961940
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3011531960
Short name T408
Test name
Test status
Simulation time 6844453808 ps
CPU time 7.49 seconds
Started Apr 23 03:14:31 PM PDT 24
Finished Apr 23 03:14:39 PM PDT 24
Peak memory 216840 kb
Host smart-715f7155-191d-4e3b-813a-9af42147e3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011531960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3011531960
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.843221439
Short name T478
Test name
Test status
Simulation time 170224006 ps
CPU time 2.83 seconds
Started Apr 23 03:14:34 PM PDT 24
Finished Apr 23 03:14:37 PM PDT 24
Peak memory 216828 kb
Host smart-3e1dc3e2-bf58-4a6d-af77-1c62e37dfb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843221439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.843221439
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3202554873
Short name T525
Test name
Test status
Simulation time 54661996 ps
CPU time 0.86 seconds
Started Apr 23 03:14:33 PM PDT 24
Finished Apr 23 03:14:34 PM PDT 24
Peak memory 206316 kb
Host smart-d58f715a-5b89-43e6-92f8-3781145ae9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202554873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3202554873
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2951584086
Short name T449
Test name
Test status
Simulation time 20528589 ps
CPU time 0.68 seconds
Started Apr 23 03:16:52 PM PDT 24
Finished Apr 23 03:16:53 PM PDT 24
Peak memory 206028 kb
Host smart-21a5aea1-fff9-476e-9b0d-e50d3bf8e7b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951584086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2951584086
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1088056051
Short name T569
Test name
Test status
Simulation time 47929746 ps
CPU time 0.72 seconds
Started Apr 23 03:16:42 PM PDT 24
Finished Apr 23 03:16:43 PM PDT 24
Peak memory 207472 kb
Host smart-91aef1d0-0339-4439-969e-cfff6655b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088056051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1088056051
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3706439958
Short name T105
Test name
Test status
Simulation time 5780279675 ps
CPU time 20.12 seconds
Started Apr 23 03:16:50 PM PDT 24
Finished Apr 23 03:17:11 PM PDT 24
Peak memory 223512 kb
Host smart-90349d79-d43c-453f-8900-8c092cac9b4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3706439958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3706439958
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2062707696
Short name T553
Test name
Test status
Simulation time 1217390342 ps
CPU time 4.23 seconds
Started Apr 23 03:16:44 PM PDT 24
Finished Apr 23 03:16:49 PM PDT 24
Peak memory 217048 kb
Host smart-bb05df01-da17-48ca-afdd-f9dc22e10069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062707696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2062707696
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1484347833
Short name T428
Test name
Test status
Simulation time 886769086 ps
CPU time 3.77 seconds
Started Apr 23 03:16:43 PM PDT 24
Finished Apr 23 03:16:47 PM PDT 24
Peak memory 216788 kb
Host smart-a48bbd98-8576-4027-a7e4-13b9b19f72f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484347833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1484347833
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2313622133
Short name T625
Test name
Test status
Simulation time 72065693 ps
CPU time 1.85 seconds
Started Apr 23 03:16:41 PM PDT 24
Finished Apr 23 03:16:43 PM PDT 24
Peak memory 216788 kb
Host smart-dc6d9933-8177-40a4-b86d-088b2fe26cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313622133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2313622133
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1915414811
Short name T558
Test name
Test status
Simulation time 18471925 ps
CPU time 0.72 seconds
Started Apr 23 03:16:48 PM PDT 24
Finished Apr 23 03:16:49 PM PDT 24
Peak memory 206348 kb
Host smart-a2dd8b7a-d029-46fd-b415-d344e5e279d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915414811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1915414811
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2522679874
Short name T329
Test name
Test status
Simulation time 6801743131 ps
CPU time 21.07 seconds
Started Apr 23 03:16:44 PM PDT 24
Finished Apr 23 03:17:06 PM PDT 24
Peak memory 234328 kb
Host smart-a177ee8b-24f8-4d8b-8d29-93e8cf355eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522679874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2522679874
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2116621444
Short name T501
Test name
Test status
Simulation time 37779861 ps
CPU time 0.72 seconds
Started Apr 23 03:17:09 PM PDT 24
Finished Apr 23 03:17:10 PM PDT 24
Peak memory 206384 kb
Host smart-c32d9ce0-2398-4ca8-b8df-bd715c09bdfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116621444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2116621444
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4251992316
Short name T479
Test name
Test status
Simulation time 16064109 ps
CPU time 0.82 seconds
Started Apr 23 03:16:52 PM PDT 24
Finished Apr 23 03:16:54 PM PDT 24
Peak memory 207160 kb
Host smart-40f0bb89-28a6-42e2-ac69-0a10f3a7e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251992316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4251992316
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3946348969
Short name T285
Test name
Test status
Simulation time 3544830888 ps
CPU time 11.12 seconds
Started Apr 23 03:17:00 PM PDT 24
Finished Apr 23 03:17:11 PM PDT 24
Peak memory 219276 kb
Host smart-4dbf43f9-1822-4342-a758-e5b3ee88aa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946348969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3946348969
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1628958679
Short name T628
Test name
Test status
Simulation time 51415880457 ps
CPU time 47.57 seconds
Started Apr 23 03:17:00 PM PDT 24
Finished Apr 23 03:17:48 PM PDT 24
Peak memory 232804 kb
Host smart-a8282583-ee56-4ca7-9128-d51674f24885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628958679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1628958679
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3670447268
Short name T269
Test name
Test status
Simulation time 2859449375 ps
CPU time 4.82 seconds
Started Apr 23 03:17:00 PM PDT 24
Finished Apr 23 03:17:05 PM PDT 24
Peak memory 220272 kb
Host smart-32fdbde3-3992-4df5-98b0-df95c8b10f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670447268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3670447268
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2277198657
Short name T535
Test name
Test status
Simulation time 1102405805 ps
CPU time 8.57 seconds
Started Apr 23 03:17:04 PM PDT 24
Finished Apr 23 03:17:13 PM PDT 24
Peak memory 220640 kb
Host smart-acb6972c-bec7-4de1-869f-da7cc6b9f1ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2277198657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2277198657
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3846313398
Short name T169
Test name
Test status
Simulation time 256364522 ps
CPU time 1.09 seconds
Started Apr 23 03:17:10 PM PDT 24
Finished Apr 23 03:17:12 PM PDT 24
Peak memory 208368 kb
Host smart-c0b78589-4271-4172-9172-02f4a75e01ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846313398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3846313398
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2501629951
Short name T3
Test name
Test status
Simulation time 4872667582 ps
CPU time 7.44 seconds
Started Apr 23 03:16:55 PM PDT 24
Finished Apr 23 03:17:03 PM PDT 24
Peak memory 216920 kb
Host smart-55f27631-6bc8-49ec-9e3f-79382b1894a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501629951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2501629951
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3156324391
Short name T617
Test name
Test status
Simulation time 316319399 ps
CPU time 7.16 seconds
Started Apr 23 03:16:54 PM PDT 24
Finished Apr 23 03:17:02 PM PDT 24
Peak memory 216900 kb
Host smart-611e42e9-0e1b-4269-8ebe-edb02ecc8501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156324391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3156324391
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.521372464
Short name T483
Test name
Test status
Simulation time 58924316 ps
CPU time 0.93 seconds
Started Apr 23 03:16:57 PM PDT 24
Finished Apr 23 03:16:58 PM PDT 24
Peak memory 207272 kb
Host smart-f340e35b-adad-4bad-81ba-100c577d55ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521372464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.521372464
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2501127281
Short name T418
Test name
Test status
Simulation time 11200273 ps
CPU time 0.73 seconds
Started Apr 23 03:17:24 PM PDT 24
Finished Apr 23 03:17:25 PM PDT 24
Peak memory 206040 kb
Host smart-a70f896b-630a-4390-8ee3-1073e9fcfaea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501127281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2501127281
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.407798479
Short name T521
Test name
Test status
Simulation time 22503612 ps
CPU time 0.77 seconds
Started Apr 23 03:17:13 PM PDT 24
Finished Apr 23 03:17:14 PM PDT 24
Peak memory 206112 kb
Host smart-695cd83b-71f6-4798-9b5d-abdc2650148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407798479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.407798479
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.456534360
Short name T300
Test name
Test status
Simulation time 3825062955 ps
CPU time 63.55 seconds
Started Apr 23 03:17:19 PM PDT 24
Finished Apr 23 03:18:23 PM PDT 24
Peak memory 233272 kb
Host smart-b2ae219b-d73a-4828-9f56-132c15a8a715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456534360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.456534360
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1342163554
Short name T255
Test name
Test status
Simulation time 3231508335 ps
CPU time 3.43 seconds
Started Apr 23 03:17:28 PM PDT 24
Finished Apr 23 03:17:32 PM PDT 24
Peak memory 219352 kb
Host smart-0c5e39d3-7be8-4d03-b9e7-b35e7eb46156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342163554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1342163554
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1043282272
Short name T519
Test name
Test status
Simulation time 889850554 ps
CPU time 4.14 seconds
Started Apr 23 03:17:20 PM PDT 24
Finished Apr 23 03:17:25 PM PDT 24
Peak memory 221820 kb
Host smart-b6761cf1-71ce-4312-8fa0-d978be4ab4a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1043282272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1043282272
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3324253303
Short name T691
Test name
Test status
Simulation time 3514504131 ps
CPU time 33.59 seconds
Started Apr 23 03:17:18 PM PDT 24
Finished Apr 23 03:17:52 PM PDT 24
Peak memory 216892 kb
Host smart-62c5e065-f7fd-4259-9b93-07b8840aef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324253303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3324253303
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3796669014
Short name T442
Test name
Test status
Simulation time 1097431946 ps
CPU time 6.77 seconds
Started Apr 23 03:17:15 PM PDT 24
Finished Apr 23 03:17:22 PM PDT 24
Peak memory 216792 kb
Host smart-ca6ae592-be5a-43f3-8d33-a5a87279e780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796669014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3796669014
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3353225604
Short name T54
Test name
Test status
Simulation time 173690995 ps
CPU time 7.89 seconds
Started Apr 23 03:17:17 PM PDT 24
Finished Apr 23 03:17:25 PM PDT 24
Peak memory 216976 kb
Host smart-153a5306-66f4-4fc8-aa34-d8955ce38e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353225604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3353225604
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2297441675
Short name T486
Test name
Test status
Simulation time 40076571 ps
CPU time 0.82 seconds
Started Apr 23 03:17:18 PM PDT 24
Finished Apr 23 03:17:19 PM PDT 24
Peak memory 206376 kb
Host smart-5cc3b1e7-6ec9-4f1e-ad81-b064f4d045d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297441675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2297441675
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3227600794
Short name T196
Test name
Test status
Simulation time 3555157207 ps
CPU time 5.9 seconds
Started Apr 23 03:17:19 PM PDT 24
Finished Apr 23 03:17:25 PM PDT 24
Peak memory 236920 kb
Host smart-113474ea-ef48-4c51-8bcb-4144849adf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227600794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3227600794
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.275213480
Short name T460
Test name
Test status
Simulation time 14089310 ps
CPU time 0.76 seconds
Started Apr 23 03:17:35 PM PDT 24
Finished Apr 23 03:17:36 PM PDT 24
Peak memory 205928 kb
Host smart-e1da032b-7a87-4764-8f04-d782d7d16978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275213480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.275213480
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.84807274
Short name T554
Test name
Test status
Simulation time 16550617 ps
CPU time 0.77 seconds
Started Apr 23 03:17:22 PM PDT 24
Finished Apr 23 03:17:23 PM PDT 24
Peak memory 207124 kb
Host smart-2b80918e-27ff-4d5e-82ec-68530fb2817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84807274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.84807274
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.230819760
Short name T137
Test name
Test status
Simulation time 2970276030 ps
CPU time 23.69 seconds
Started Apr 23 03:17:28 PM PDT 24
Finished Apr 23 03:17:52 PM PDT 24
Peak memory 232672 kb
Host smart-de34a414-629a-4023-b20a-fdc445eeea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230819760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.230819760
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3830495713
Short name T326
Test name
Test status
Simulation time 91515698275 ps
CPU time 39.2 seconds
Started Apr 23 03:17:27 PM PDT 24
Finished Apr 23 03:18:07 PM PDT 24
Peak memory 221216 kb
Host smart-a84a250c-2245-43cc-950b-38e2fda0f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830495713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3830495713
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3483892427
Short name T529
Test name
Test status
Simulation time 327298277 ps
CPU time 6.14 seconds
Started Apr 23 03:17:33 PM PDT 24
Finished Apr 23 03:17:39 PM PDT 24
Peak memory 223488 kb
Host smart-d6c76e3a-75ad-46ba-a49a-c1fe786148a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3483892427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3483892427
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1912573957
Short name T621
Test name
Test status
Simulation time 52020151977 ps
CPU time 70.77 seconds
Started Apr 23 03:17:24 PM PDT 24
Finished Apr 23 03:18:36 PM PDT 24
Peak memory 216868 kb
Host smart-5b581459-23b6-4da1-beda-dd9c883be1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912573957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1912573957
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2631077532
Short name T646
Test name
Test status
Simulation time 137783839 ps
CPU time 1.57 seconds
Started Apr 23 03:17:24 PM PDT 24
Finished Apr 23 03:17:26 PM PDT 24
Peak memory 208388 kb
Host smart-e630c405-8f82-4bc6-a313-8d558048fe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631077532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2631077532
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1339187107
Short name T496
Test name
Test status
Simulation time 179828352 ps
CPU time 5.66 seconds
Started Apr 23 03:17:27 PM PDT 24
Finished Apr 23 03:17:34 PM PDT 24
Peak memory 216780 kb
Host smart-1029909f-606b-45b6-9c00-5585abb559e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339187107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1339187107
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1307310665
Short name T416
Test name
Test status
Simulation time 208413238 ps
CPU time 0.97 seconds
Started Apr 23 03:17:23 PM PDT 24
Finished Apr 23 03:17:24 PM PDT 24
Peak memory 207380 kb
Host smart-3fa502f3-ab0b-4b79-a6a6-5cfe86d5bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307310665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1307310665
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1843415825
Short name T194
Test name
Test status
Simulation time 2580586641 ps
CPU time 4.09 seconds
Started Apr 23 03:17:33 PM PDT 24
Finished Apr 23 03:17:37 PM PDT 24
Peak memory 217012 kb
Host smart-97606965-304f-4461-ac4e-8aef4cd93fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843415825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1843415825
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3515510141
Short name T684
Test name
Test status
Simulation time 18525262 ps
CPU time 0.73 seconds
Started Apr 23 03:17:54 PM PDT 24
Finished Apr 23 03:17:55 PM PDT 24
Peak memory 206028 kb
Host smart-c0b02f39-bea3-4ecd-b495-b4adca9760b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515510141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3515510141
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1784321646
Short name T608
Test name
Test status
Simulation time 18994360 ps
CPU time 0.79 seconds
Started Apr 23 03:17:36 PM PDT 24
Finished Apr 23 03:17:37 PM PDT 24
Peak memory 207160 kb
Host smart-c5c5f04b-b3b5-42a4-b6c3-7d8fac05b716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784321646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1784321646
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2092650810
Short name T594
Test name
Test status
Simulation time 11999923492 ps
CPU time 17.5 seconds
Started Apr 23 03:17:44 PM PDT 24
Finished Apr 23 03:18:02 PM PDT 24
Peak memory 220912 kb
Host smart-ff234dcb-8701-44f9-9985-6c529e1f9d98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2092650810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2092650810
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1630442944
Short name T642
Test name
Test status
Simulation time 2509833504 ps
CPU time 2.1 seconds
Started Apr 23 03:17:37 PM PDT 24
Finished Apr 23 03:17:40 PM PDT 24
Peak memory 208516 kb
Host smart-5ac279f8-a3f0-4d63-80ca-43e82685f907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630442944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1630442944
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3581980445
Short name T55
Test name
Test status
Simulation time 71417040 ps
CPU time 1.44 seconds
Started Apr 23 03:17:45 PM PDT 24
Finished Apr 23 03:17:47 PM PDT 24
Peak memory 216832 kb
Host smart-f3a32238-a51f-432e-a4af-acaaeeb01351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581980445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3581980445
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3977096554
Short name T580
Test name
Test status
Simulation time 72687764 ps
CPU time 0.82 seconds
Started Apr 23 03:17:42 PM PDT 24
Finished Apr 23 03:17:43 PM PDT 24
Peak memory 206360 kb
Host smart-d7c87b7f-bfe1-43e2-aa0d-6eb70179da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977096554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3977096554
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2321150176
Short name T345
Test name
Test status
Simulation time 4484051955 ps
CPU time 5.41 seconds
Started Apr 23 03:17:44 PM PDT 24
Finished Apr 23 03:17:50 PM PDT 24
Peak memory 223352 kb
Host smart-c8119027-9eaa-4ebb-9573-fafb8a7b8365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321150176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2321150176
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.308616182
Short name T504
Test name
Test status
Simulation time 43888786 ps
CPU time 0.73 seconds
Started Apr 23 03:18:05 PM PDT 24
Finished Apr 23 03:18:06 PM PDT 24
Peak memory 206056 kb
Host smart-a9586932-21d0-487d-8e8e-e8112af23acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308616182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.308616182
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2324410978
Short name T491
Test name
Test status
Simulation time 28625169 ps
CPU time 0.8 seconds
Started Apr 23 03:17:51 PM PDT 24
Finished Apr 23 03:17:53 PM PDT 24
Peak memory 207144 kb
Host smart-34d582df-302f-4ff8-b9d2-7385a3728fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324410978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2324410978
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.985079329
Short name T717
Test name
Test status
Simulation time 8871212260 ps
CPU time 43.64 seconds
Started Apr 23 03:17:59 PM PDT 24
Finished Apr 23 03:18:43 PM PDT 24
Peak memory 241232 kb
Host smart-837afe4b-51b4-495a-a89a-4ec620a40293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985079329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.985079329
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.866155796
Short name T46
Test name
Test status
Simulation time 1523398599 ps
CPU time 18.51 seconds
Started Apr 23 03:17:59 PM PDT 24
Finished Apr 23 03:18:18 PM PDT 24
Peak memory 219244 kb
Host smart-d9b03753-ba44-4e16-b59e-3ce586506e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866155796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.866155796
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2001068921
Short name T233
Test name
Test status
Simulation time 12086477554 ps
CPU time 27.22 seconds
Started Apr 23 03:18:01 PM PDT 24
Finished Apr 23 03:18:28 PM PDT 24
Peak memory 219484 kb
Host smart-a708e274-a939-4f17-82fe-dd5125b75fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001068921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2001068921
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3803667737
Short name T361
Test name
Test status
Simulation time 166387843 ps
CPU time 3.28 seconds
Started Apr 23 03:17:55 PM PDT 24
Finished Apr 23 03:17:59 PM PDT 24
Peak memory 217320 kb
Host smart-ce720edf-e5ef-48b5-9e8b-481e8b2ba456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803667737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3803667737
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3337341256
Short name T605
Test name
Test status
Simulation time 1037232628 ps
CPU time 5.15 seconds
Started Apr 23 03:18:00 PM PDT 24
Finished Apr 23 03:18:05 PM PDT 24
Peak memory 223512 kb
Host smart-ae97a802-05f1-452c-8f55-f39b6ba2e294
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3337341256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3337341256
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2222437362
Short name T384
Test name
Test status
Simulation time 1200530378 ps
CPU time 17.13 seconds
Started Apr 23 03:17:56 PM PDT 24
Finished Apr 23 03:18:13 PM PDT 24
Peak memory 216940 kb
Host smart-13fb17bc-4f3f-4bcf-8aee-8540c2f9435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222437362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2222437362
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1295214204
Short name T716
Test name
Test status
Simulation time 14029478434 ps
CPU time 16.16 seconds
Started Apr 23 03:17:54 PM PDT 24
Finished Apr 23 03:18:11 PM PDT 24
Peak memory 216888 kb
Host smart-f79b899b-8533-4cc2-81cb-82faf941c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295214204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1295214204
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2757381513
Short name T706
Test name
Test status
Simulation time 41411129 ps
CPU time 1.26 seconds
Started Apr 23 03:17:56 PM PDT 24
Finished Apr 23 03:17:58 PM PDT 24
Peak memory 216672 kb
Host smart-0437b1ea-8353-4169-bc5f-74e2aac85f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757381513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2757381513
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.302840960
Short name T494
Test name
Test status
Simulation time 17107893 ps
CPU time 0.71 seconds
Started Apr 23 03:17:54 PM PDT 24
Finished Apr 23 03:17:55 PM PDT 24
Peak memory 206304 kb
Host smart-2350dcad-80da-4e1f-b0ae-92c18ab1ec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302840960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.302840960
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2893632220
Short name T43
Test name
Test status
Simulation time 31107480922 ps
CPU time 25.25 seconds
Started Apr 23 03:17:58 PM PDT 24
Finished Apr 23 03:18:23 PM PDT 24
Peak memory 230516 kb
Host smart-4c262db9-df19-40d8-ad1d-98f6bb87dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893632220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2893632220
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3638289798
Short name T456
Test name
Test status
Simulation time 46784756 ps
CPU time 0.74 seconds
Started Apr 23 03:18:06 PM PDT 24
Finished Apr 23 03:18:07 PM PDT 24
Peak memory 206104 kb
Host smart-c362926c-5c21-40b2-bb86-aaef48afe6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638289798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3638289798
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3452556380
Short name T223
Test name
Test status
Simulation time 7386632625 ps
CPU time 7.94 seconds
Started Apr 23 03:18:10 PM PDT 24
Finished Apr 23 03:18:18 PM PDT 24
Peak memory 219476 kb
Host smart-a5c82951-4df3-4fcb-a1ff-3910de87462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452556380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3452556380
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1186397074
Short name T161
Test name
Test status
Simulation time 205452947 ps
CPU time 3.86 seconds
Started Apr 23 03:18:19 PM PDT 24
Finished Apr 23 03:18:23 PM PDT 24
Peak memory 220868 kb
Host smart-924e7e8b-48f2-4cd9-9cea-6cf44cfe595c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1186397074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1186397074
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.771118681
Short name T39
Test name
Test status
Simulation time 195861949 ps
CPU time 1.11 seconds
Started Apr 23 03:18:21 PM PDT 24
Finished Apr 23 03:18:22 PM PDT 24
Peak memory 208472 kb
Host smart-b0c836dd-1bed-4c22-a4cf-41a9533ab9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771118681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.771118681
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4193465517
Short name T652
Test name
Test status
Simulation time 3506914167 ps
CPU time 5.35 seconds
Started Apr 23 03:18:07 PM PDT 24
Finished Apr 23 03:18:13 PM PDT 24
Peak memory 216940 kb
Host smart-6ac39a40-5010-439a-a8a2-d2d219a69220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193465517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4193465517
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1452833980
Short name T696
Test name
Test status
Simulation time 30962149755 ps
CPU time 14.09 seconds
Started Apr 23 03:18:05 PM PDT 24
Finished Apr 23 03:18:20 PM PDT 24
Peak memory 216868 kb
Host smart-c09c9612-6e71-4913-8767-5305741540c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452833980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1452833980
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.983305928
Short name T527
Test name
Test status
Simulation time 15558268 ps
CPU time 0.9 seconds
Started Apr 23 03:18:10 PM PDT 24
Finished Apr 23 03:18:11 PM PDT 24
Peak memory 207396 kb
Host smart-5e3fd966-af3b-461f-8719-831b4eb00776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983305928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.983305928
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2517817251
Short name T629
Test name
Test status
Simulation time 129536237 ps
CPU time 0.89 seconds
Started Apr 23 03:18:10 PM PDT 24
Finished Apr 23 03:18:11 PM PDT 24
Peak memory 207372 kb
Host smart-33a9ebcc-28b5-4519-87ea-1fc19e5b5810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517817251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2517817251
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2667793752
Short name T317
Test name
Test status
Simulation time 8270194951 ps
CPU time 21.49 seconds
Started Apr 23 03:18:15 PM PDT 24
Finished Apr 23 03:18:36 PM PDT 24
Peak memory 222772 kb
Host smart-d83492fe-a530-4277-94c4-d0c3d2d2dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667793752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2667793752
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3829252028
Short name T435
Test name
Test status
Simulation time 14589270 ps
CPU time 0.71 seconds
Started Apr 23 03:18:39 PM PDT 24
Finished Apr 23 03:18:40 PM PDT 24
Peak memory 205988 kb
Host smart-5c46b630-ddc1-4676-a223-5b54723b8d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829252028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3829252028
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1897329475
Short name T606
Test name
Test status
Simulation time 15345729 ps
CPU time 0.71 seconds
Started Apr 23 03:18:24 PM PDT 24
Finished Apr 23 03:18:25 PM PDT 24
Peak memory 206148 kb
Host smart-bc4a501e-601f-4397-a23f-00b6803f7d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897329475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1897329475
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.66235531
Short name T498
Test name
Test status
Simulation time 82757320 ps
CPU time 4.07 seconds
Started Apr 23 03:18:35 PM PDT 24
Finished Apr 23 03:18:39 PM PDT 24
Peak memory 222976 kb
Host smart-7e460225-c0a1-4fd2-8f94-be2d0454f79e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66235531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direc
t.66235531
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4030303065
Short name T379
Test name
Test status
Simulation time 16484919644 ps
CPU time 39 seconds
Started Apr 23 03:18:26 PM PDT 24
Finished Apr 23 03:19:06 PM PDT 24
Peak memory 221544 kb
Host smart-adb3ab89-e172-4b60-a243-6431b5284284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030303065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4030303065
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3508446961
Short name T586
Test name
Test status
Simulation time 7882884250 ps
CPU time 7.8 seconds
Started Apr 23 03:18:27 PM PDT 24
Finished Apr 23 03:18:35 PM PDT 24
Peak memory 216900 kb
Host smart-825bd084-4bc6-4d87-bc3a-5bd4b5787b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508446961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3508446961
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3709476693
Short name T457
Test name
Test status
Simulation time 75231533 ps
CPU time 1.36 seconds
Started Apr 23 03:18:24 PM PDT 24
Finished Apr 23 03:18:26 PM PDT 24
Peak memory 216788 kb
Host smart-c471afbd-083d-4733-a0f7-998876af76de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709476693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3709476693
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.164735192
Short name T662
Test name
Test status
Simulation time 245245923 ps
CPU time 0.95 seconds
Started Apr 23 03:18:26 PM PDT 24
Finished Apr 23 03:18:27 PM PDT 24
Peak memory 207384 kb
Host smart-81be9a40-092e-4f2d-8cb7-2980384aee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164735192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.164735192
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3915790922
Short name T278
Test name
Test status
Simulation time 34174034350 ps
CPU time 27.34 seconds
Started Apr 23 03:18:29 PM PDT 24
Finished Apr 23 03:18:56 PM PDT 24
Peak memory 236620 kb
Host smart-c20cb535-cb16-41c1-afa0-27e5db7ab94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915790922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3915790922
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4177435639
Short name T655
Test name
Test status
Simulation time 12551801 ps
CPU time 0.73 seconds
Started Apr 23 03:18:57 PM PDT 24
Finished Apr 23 03:18:58 PM PDT 24
Peak memory 206036 kb
Host smart-9f86cfdd-a1ef-4a48-82fa-0ba61d6c447e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177435639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4177435639
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1016517605
Short name T712
Test name
Test status
Simulation time 49190544 ps
CPU time 0.73 seconds
Started Apr 23 03:18:39 PM PDT 24
Finished Apr 23 03:18:40 PM PDT 24
Peak memory 205900 kb
Host smart-8de85b9d-76cb-4055-8824-2f1f2c408e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016517605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1016517605
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3965659440
Short name T365
Test name
Test status
Simulation time 6060361933 ps
CPU time 36.37 seconds
Started Apr 23 03:18:51 PM PDT 24
Finished Apr 23 03:19:28 PM PDT 24
Peak memory 233276 kb
Host smart-ad3e47b5-a586-40bc-9301-7fb0fe904cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965659440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3965659440
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3947091831
Short name T186
Test name
Test status
Simulation time 432913089 ps
CPU time 6.09 seconds
Started Apr 23 03:18:43 PM PDT 24
Finished Apr 23 03:18:50 PM PDT 24
Peak memory 221316 kb
Host smart-17a00e8c-b8e9-4b6d-be9d-3d4708342d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947091831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3947091831
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2249562870
Short name T5
Test name
Test status
Simulation time 992081096 ps
CPU time 5.9 seconds
Started Apr 23 03:18:51 PM PDT 24
Finished Apr 23 03:18:57 PM PDT 24
Peak memory 220736 kb
Host smart-f66adb85-2fde-430c-b2ba-73bef51ab746
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249562870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2249562870
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1184232194
Short name T354
Test name
Test status
Simulation time 279961525 ps
CPU time 1.05 seconds
Started Apr 23 03:19:12 PM PDT 24
Finished Apr 23 03:19:14 PM PDT 24
Peak memory 207592 kb
Host smart-304cc8d3-5fd9-4c4a-b9af-a9c5302c1261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184232194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1184232194
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3052028229
Short name T20
Test name
Test status
Simulation time 2389912422 ps
CPU time 14.2 seconds
Started Apr 23 03:18:44 PM PDT 24
Finished Apr 23 03:18:59 PM PDT 24
Peak memory 216968 kb
Host smart-7f0a96b6-5344-49d9-9265-0fac408efc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052028229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3052028229
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3852332515
Short name T715
Test name
Test status
Simulation time 589248920 ps
CPU time 2.36 seconds
Started Apr 23 03:18:44 PM PDT 24
Finished Apr 23 03:18:47 PM PDT 24
Peak memory 216808 kb
Host smart-31c6fe03-3fc0-401d-a51a-5337b5939aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852332515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3852332515
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.778654234
Short name T406
Test name
Test status
Simulation time 102078150 ps
CPU time 0.91 seconds
Started Apr 23 03:18:45 PM PDT 24
Finished Apr 23 03:18:46 PM PDT 24
Peak memory 207352 kb
Host smart-db50fedb-e0ae-4400-9aea-a01b8963f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778654234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.778654234
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4123595598
Short name T657
Test name
Test status
Simulation time 14830081 ps
CPU time 0.73 seconds
Started Apr 23 03:19:09 PM PDT 24
Finished Apr 23 03:19:10 PM PDT 24
Peak memory 206360 kb
Host smart-5408c269-2a43-4523-9008-d8dd8b03c716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123595598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4123595598
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1450624814
Short name T24
Test name
Test status
Simulation time 270989951 ps
CPU time 2.86 seconds
Started Apr 23 03:19:03 PM PDT 24
Finished Apr 23 03:19:06 PM PDT 24
Peak memory 219244 kb
Host smart-f5e22637-c2bb-4dc5-ac70-908d180ec464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450624814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1450624814
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.493453531
Short name T673
Test name
Test status
Simulation time 142557654 ps
CPU time 0.81 seconds
Started Apr 23 03:18:55 PM PDT 24
Finished Apr 23 03:18:56 PM PDT 24
Peak memory 207144 kb
Host smart-e869beca-603d-42a5-bfbe-c078909bc0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493453531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.493453531
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3946096689
Short name T364
Test name
Test status
Simulation time 16597052346 ps
CPU time 67.41 seconds
Started Apr 23 03:19:00 PM PDT 24
Finished Apr 23 03:20:08 PM PDT 24
Peak memory 249712 kb
Host smart-cd3e4835-e06b-4af7-ac86-bcd3edfe298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946096689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3946096689
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.242658395
Short name T511
Test name
Test status
Simulation time 1338311555 ps
CPU time 7.07 seconds
Started Apr 23 03:19:05 PM PDT 24
Finished Apr 23 03:19:12 PM PDT 24
Peak memory 220612 kb
Host smart-997dd491-5834-4d59-b1e2-14d59eed565f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242658395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.242658395
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2480894312
Short name T476
Test name
Test status
Simulation time 29392107239 ps
CPU time 24.56 seconds
Started Apr 23 03:18:56 PM PDT 24
Finished Apr 23 03:19:21 PM PDT 24
Peak memory 217980 kb
Host smart-8e6b048b-f383-4e8e-8435-cd919467c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480894312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2480894312
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2113723339
Short name T545
Test name
Test status
Simulation time 237220053 ps
CPU time 1.47 seconds
Started Apr 23 03:19:02 PM PDT 24
Finished Apr 23 03:19:04 PM PDT 24
Peak memory 216908 kb
Host smart-0dcb9c08-5ace-45d4-82cc-47a7327d51f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113723339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2113723339
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1857682949
Short name T588
Test name
Test status
Simulation time 108546771 ps
CPU time 0.96 seconds
Started Apr 23 03:18:56 PM PDT 24
Finished Apr 23 03:18:57 PM PDT 24
Peak memory 207328 kb
Host smart-61a2e773-a8bb-417a-819f-a89c76e04176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857682949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1857682949
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.796691216
Short name T585
Test name
Test status
Simulation time 41171707 ps
CPU time 0.73 seconds
Started Apr 23 03:15:02 PM PDT 24
Finished Apr 23 03:15:04 PM PDT 24
Peak memory 206004 kb
Host smart-c80f86fb-6b6c-4f05-9591-e9be3306483e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796691216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.796691216
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.121845881
Short name T83
Test name
Test status
Simulation time 756275024 ps
CPU time 3.28 seconds
Started Apr 23 03:14:54 PM PDT 24
Finished Apr 23 03:14:58 PM PDT 24
Peak memory 219464 kb
Host smart-d0297ef7-6480-472d-873b-eff05cbd8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121845881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.121845881
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1373162119
Short name T686
Test name
Test status
Simulation time 53817224 ps
CPU time 0.74 seconds
Started Apr 23 03:14:42 PM PDT 24
Finished Apr 23 03:14:43 PM PDT 24
Peak memory 207472 kb
Host smart-0fc5f3d7-1c73-4738-bcb1-aaa0981cc411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373162119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1373162119
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1396248666
Short name T719
Test name
Test status
Simulation time 12440323252 ps
CPU time 75.95 seconds
Started Apr 23 03:14:54 PM PDT 24
Finished Apr 23 03:16:10 PM PDT 24
Peak memory 238200 kb
Host smart-e4d551d9-3a5a-456e-822e-ce611e61c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396248666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1396248666
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3120263682
Short name T277
Test name
Test status
Simulation time 7168207138 ps
CPU time 30.46 seconds
Started Apr 23 03:14:59 PM PDT 24
Finished Apr 23 03:15:30 PM PDT 24
Peak memory 219612 kb
Host smart-91558931-e936-4e8c-bd59-373035819ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120263682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3120263682
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2373668787
Short name T325
Test name
Test status
Simulation time 9021635009 ps
CPU time 29.89 seconds
Started Apr 23 03:14:46 PM PDT 24
Finished Apr 23 03:15:16 PM PDT 24
Peak memory 224904 kb
Host smart-4c4c1ca6-e228-40a2-a606-d16e0cdd2cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373668787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2373668787
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1493407615
Short name T515
Test name
Test status
Simulation time 406071571 ps
CPU time 3.42 seconds
Started Apr 23 03:14:53 PM PDT 24
Finished Apr 23 03:14:57 PM PDT 24
Peak memory 219416 kb
Host smart-d0cc4cf3-9708-420d-8b2b-fee926d39091
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493407615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1493407615
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2500174304
Short name T392
Test name
Test status
Simulation time 37598139639 ps
CPU time 55.47 seconds
Started Apr 23 03:14:46 PM PDT 24
Finished Apr 23 03:15:41 PM PDT 24
Peak memory 222472 kb
Host smart-45df8ca2-e1c9-42ad-bc6e-29f66bf0b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500174304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2500174304
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2395359109
Short name T503
Test name
Test status
Simulation time 8302874340 ps
CPU time 11.46 seconds
Started Apr 23 03:14:44 PM PDT 24
Finished Apr 23 03:14:56 PM PDT 24
Peak memory 216936 kb
Host smart-4e3c1a0a-f2a0-4efa-a94c-c04a101373ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395359109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2395359109
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2590571143
Short name T13
Test name
Test status
Simulation time 250960455 ps
CPU time 6.45 seconds
Started Apr 23 03:14:47 PM PDT 24
Finished Apr 23 03:14:54 PM PDT 24
Peak memory 216972 kb
Host smart-aa5b1656-00d9-4fa6-a56a-b73da0a577bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590571143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2590571143
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1186229725
Short name T488
Test name
Test status
Simulation time 15600124 ps
CPU time 0.73 seconds
Started Apr 23 03:14:43 PM PDT 24
Finished Apr 23 03:14:44 PM PDT 24
Peak memory 206312 kb
Host smart-e2fe4d96-2662-4b07-806a-9497fcbadd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186229725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1186229725
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3217665689
Short name T623
Test name
Test status
Simulation time 48095848 ps
CPU time 0.7 seconds
Started Apr 23 03:19:27 PM PDT 24
Finished Apr 23 03:19:28 PM PDT 24
Peak memory 206012 kb
Host smart-84e9ba09-2e5d-4e96-9fba-8531d3385383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217665689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3217665689
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2249472802
Short name T564
Test name
Test status
Simulation time 47314428 ps
CPU time 0.83 seconds
Started Apr 23 03:19:08 PM PDT 24
Finished Apr 23 03:19:10 PM PDT 24
Peak memory 206444 kb
Host smart-086f74dd-422a-4175-8279-bf1ce0055c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249472802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2249472802
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2893304549
Short name T640
Test name
Test status
Simulation time 13497898709 ps
CPU time 52.69 seconds
Started Apr 23 03:19:16 PM PDT 24
Finished Apr 23 03:20:09 PM PDT 24
Peak memory 249652 kb
Host smart-74bd8e37-a945-40f6-ac57-90451d35f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893304549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2893304549
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3923493220
Short name T611
Test name
Test status
Simulation time 98852693 ps
CPU time 3.15 seconds
Started Apr 23 03:19:14 PM PDT 24
Finished Apr 23 03:19:18 PM PDT 24
Peak memory 222896 kb
Host smart-7249caa6-e73d-44a3-a826-793bd5c132b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923493220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3923493220
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.786058449
Short name T701
Test name
Test status
Simulation time 633412204 ps
CPU time 7.2 seconds
Started Apr 23 03:19:13 PM PDT 24
Finished Apr 23 03:19:20 PM PDT 24
Peak memory 223492 kb
Host smart-d6391325-00a3-4e79-91cb-769b72a3c89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786058449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.786058449
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3044456445
Short name T63
Test name
Test status
Simulation time 456493755 ps
CPU time 5.69 seconds
Started Apr 23 03:19:17 PM PDT 24
Finished Apr 23 03:19:23 PM PDT 24
Peak memory 219488 kb
Host smart-f712ce70-02ea-4907-96f7-5999f0824a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044456445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3044456445
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1718761437
Short name T591
Test name
Test status
Simulation time 4417894063 ps
CPU time 14.14 seconds
Started Apr 23 03:19:17 PM PDT 24
Finished Apr 23 03:19:32 PM PDT 24
Peak memory 220644 kb
Host smart-8aca3194-dee9-4f2f-a476-cbe71e465966
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1718761437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1718761437
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2142666555
Short name T385
Test name
Test status
Simulation time 30683211613 ps
CPU time 16.94 seconds
Started Apr 23 03:19:09 PM PDT 24
Finished Apr 23 03:19:26 PM PDT 24
Peak memory 217048 kb
Host smart-ea753668-14b2-48ea-94f9-f25472a02f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142666555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2142666555
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3275752662
Short name T539
Test name
Test status
Simulation time 693725987 ps
CPU time 4.09 seconds
Started Apr 23 03:19:15 PM PDT 24
Finished Apr 23 03:19:20 PM PDT 24
Peak memory 216800 kb
Host smart-a7c32f19-c209-4ab7-9b48-514bf1e4c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275752662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3275752662
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1177821515
Short name T618
Test name
Test status
Simulation time 577881058 ps
CPU time 7.28 seconds
Started Apr 23 03:19:10 PM PDT 24
Finished Apr 23 03:19:18 PM PDT 24
Peak memory 216760 kb
Host smart-ec84ce66-c2f8-483d-8557-21e394f593f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177821515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1177821515
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.634840723
Short name T703
Test name
Test status
Simulation time 27908294 ps
CPU time 0.75 seconds
Started Apr 23 03:19:12 PM PDT 24
Finished Apr 23 03:19:13 PM PDT 24
Peak memory 206340 kb
Host smart-395504fb-00a3-4e0b-b9f1-d22267fc0873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634840723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.634840723
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.85734972
Short name T433
Test name
Test status
Simulation time 34005371 ps
CPU time 0.75 seconds
Started Apr 23 03:19:29 PM PDT 24
Finished Apr 23 03:19:30 PM PDT 24
Peak memory 206012 kb
Host smart-59b46530-7cfc-4dca-b8e7-3eb6d432eed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85734972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.85734972
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.765617756
Short name T678
Test name
Test status
Simulation time 23608721 ps
CPU time 0.81 seconds
Started Apr 23 03:19:23 PM PDT 24
Finished Apr 23 03:19:24 PM PDT 24
Peak memory 207164 kb
Host smart-f744c10d-7f6f-44af-bd7d-12e2a342ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765617756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.765617756
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1531694981
Short name T659
Test name
Test status
Simulation time 176473736 ps
CPU time 4.48 seconds
Started Apr 23 03:19:30 PM PDT 24
Finished Apr 23 03:19:35 PM PDT 24
Peak memory 222944 kb
Host smart-49091a24-3018-42c0-a7c3-4a25d72c3d31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1531694981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1531694981
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3351668631
Short name T386
Test name
Test status
Simulation time 1305920264 ps
CPU time 15.69 seconds
Started Apr 23 03:19:27 PM PDT 24
Finished Apr 23 03:19:43 PM PDT 24
Peak memory 216756 kb
Host smart-4132090a-dbfb-4899-9493-e8d625cbf4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351668631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3351668631
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1324004246
Short name T465
Test name
Test status
Simulation time 787896175 ps
CPU time 3.05 seconds
Started Apr 23 03:19:24 PM PDT 24
Finished Apr 23 03:19:28 PM PDT 24
Peak memory 216592 kb
Host smart-63a1a290-51d0-4220-8a15-5e134f2b0107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324004246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1324004246
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1041543959
Short name T619
Test name
Test status
Simulation time 44641687 ps
CPU time 0.88 seconds
Started Apr 23 03:19:26 PM PDT 24
Finished Apr 23 03:19:27 PM PDT 24
Peak memory 207384 kb
Host smart-b2b6d148-10f9-471d-a3f4-f2bed6909994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041543959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1041543959
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2071984304
Short name T531
Test name
Test status
Simulation time 292282845 ps
CPU time 0.95 seconds
Started Apr 23 03:19:27 PM PDT 24
Finished Apr 23 03:19:29 PM PDT 24
Peak memory 207376 kb
Host smart-ee44ca89-d4b1-48b5-9dc5-de85eb94c917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071984304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2071984304
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1974068504
Short name T635
Test name
Test status
Simulation time 13485557 ps
CPU time 0.72 seconds
Started Apr 23 03:19:42 PM PDT 24
Finished Apr 23 03:19:43 PM PDT 24
Peak memory 206060 kb
Host smart-821708c2-5776-4091-9569-ab230400b8ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974068504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1974068504
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.163987915
Short name T570
Test name
Test status
Simulation time 56374700 ps
CPU time 0.78 seconds
Started Apr 23 03:19:30 PM PDT 24
Finished Apr 23 03:19:31 PM PDT 24
Peak memory 207144 kb
Host smart-bffeb37d-ea8f-4834-b5ba-1e1e5168e819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163987915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.163987915
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.5159910
Short name T544
Test name
Test status
Simulation time 311277612 ps
CPU time 2.41 seconds
Started Apr 23 03:19:33 PM PDT 24
Finished Apr 23 03:19:36 PM PDT 24
Peak memory 219072 kb
Host smart-79ad27e2-1583-4ab3-8149-e8aae31cec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5159910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.5159910
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3924636838
Short name T630
Test name
Test status
Simulation time 1670131435 ps
CPU time 11.09 seconds
Started Apr 23 03:19:40 PM PDT 24
Finished Apr 23 03:19:51 PM PDT 24
Peak memory 222780 kb
Host smart-78aea8f4-887b-4367-86df-e456d9c91ab0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3924636838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3924636838
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1586279191
Short name T649
Test name
Test status
Simulation time 2501116302 ps
CPU time 44.48 seconds
Started Apr 23 03:19:28 PM PDT 24
Finished Apr 23 03:20:13 PM PDT 24
Peak memory 216968 kb
Host smart-1f2ba4b5-6467-4b95-9951-591b61b630b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586279191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1586279191
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4007838398
Short name T472
Test name
Test status
Simulation time 4137995519 ps
CPU time 13.2 seconds
Started Apr 23 03:19:31 PM PDT 24
Finished Apr 23 03:19:44 PM PDT 24
Peak memory 216812 kb
Host smart-3126ded1-93f1-4a58-83ff-4dbcd247cc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007838398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4007838398
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.666337012
Short name T518
Test name
Test status
Simulation time 246683422 ps
CPU time 0.8 seconds
Started Apr 23 03:19:32 PM PDT 24
Finished Apr 23 03:19:33 PM PDT 24
Peak memory 206420 kb
Host smart-1e9e96ab-21be-40bc-8eed-1d00df666b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666337012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.666337012
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2408731591
Short name T576
Test name
Test status
Simulation time 31307281 ps
CPU time 0.75 seconds
Started Apr 23 03:19:33 PM PDT 24
Finished Apr 23 03:19:34 PM PDT 24
Peak memory 206320 kb
Host smart-e4b96e7e-4a68-408f-b07c-572816dcd5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408731591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2408731591
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1147804103
Short name T524
Test name
Test status
Simulation time 148730316 ps
CPU time 0.72 seconds
Started Apr 23 03:19:53 PM PDT 24
Finished Apr 23 03:19:55 PM PDT 24
Peak memory 205480 kb
Host smart-0dcb857e-9577-4b2d-9d93-2c581d3d2339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147804103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1147804103
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2189113520
Short name T403
Test name
Test status
Simulation time 29286071 ps
CPU time 0.8 seconds
Started Apr 23 03:19:44 PM PDT 24
Finished Apr 23 03:19:45 PM PDT 24
Peak memory 207168 kb
Host smart-001c485e-4fa5-45b3-95b5-3eae9f28275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189113520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2189113520
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2620570441
Short name T697
Test name
Test status
Simulation time 352748657 ps
CPU time 3.78 seconds
Started Apr 23 03:19:50 PM PDT 24
Finished Apr 23 03:19:54 PM PDT 24
Peak memory 224876 kb
Host smart-81ac289e-ca05-4675-9f2f-8af3426272a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620570441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2620570441
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.214717911
Short name T347
Test name
Test status
Simulation time 3932140779 ps
CPU time 4.92 seconds
Started Apr 23 03:19:50 PM PDT 24
Finished Apr 23 03:19:56 PM PDT 24
Peak memory 223916 kb
Host smart-5ef5552c-d131-41b2-a0f0-408b595f4ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214717911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.214717911
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.228092632
Short name T624
Test name
Test status
Simulation time 180887097 ps
CPU time 4.78 seconds
Started Apr 23 03:19:52 PM PDT 24
Finished Apr 23 03:19:58 PM PDT 24
Peak memory 223460 kb
Host smart-66f68ef4-6385-4c0e-8e8d-782f8b1006e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=228092632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.228092632
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1099247813
Short name T380
Test name
Test status
Simulation time 3944813886 ps
CPU time 21.62 seconds
Started Apr 23 03:19:48 PM PDT 24
Finished Apr 23 03:20:11 PM PDT 24
Peak memory 216884 kb
Host smart-1d509a08-4336-48d7-8103-0a2b83c5d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099247813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1099247813
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4256390970
Short name T656
Test name
Test status
Simulation time 1420893524 ps
CPU time 8.52 seconds
Started Apr 23 03:19:44 PM PDT 24
Finished Apr 23 03:19:53 PM PDT 24
Peak memory 216800 kb
Host smart-e15d69ce-cc4a-40b5-8f8b-1afe42c20a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256390970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4256390970
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1067677061
Short name T688
Test name
Test status
Simulation time 25901418 ps
CPU time 0.81 seconds
Started Apr 23 03:19:47 PM PDT 24
Finished Apr 23 03:19:48 PM PDT 24
Peak memory 207104 kb
Host smart-94ea78fb-b166-4d8d-91e2-bc819b23ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067677061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1067677061
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1152219385
Short name T482
Test name
Test status
Simulation time 61334985 ps
CPU time 0.85 seconds
Started Apr 23 03:19:47 PM PDT 24
Finished Apr 23 03:19:49 PM PDT 24
Peak memory 206316 kb
Host smart-241a3968-9293-44bc-81cd-17d456666005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152219385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1152219385
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1384180438
Short name T480
Test name
Test status
Simulation time 45215744 ps
CPU time 0.72 seconds
Started Apr 23 03:20:05 PM PDT 24
Finished Apr 23 03:20:06 PM PDT 24
Peak memory 205436 kb
Host smart-1262d68b-4d6c-4715-9099-37b4d1dfee59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384180438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1384180438
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1322246554
Short name T682
Test name
Test status
Simulation time 20317978 ps
CPU time 0.76 seconds
Started Apr 23 03:19:57 PM PDT 24
Finished Apr 23 03:19:58 PM PDT 24
Peak memory 207496 kb
Host smart-29826cad-b11b-4ff8-ae5a-b63134dac967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322246554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1322246554
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.272875896
Short name T681
Test name
Test status
Simulation time 7488262256 ps
CPU time 51.73 seconds
Started Apr 23 03:20:02 PM PDT 24
Finished Apr 23 03:20:54 PM PDT 24
Peak memory 225112 kb
Host smart-75b12e1a-0a3f-4b51-ab96-c00c89a9a16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272875896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.272875896
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1150068018
Short name T312
Test name
Test status
Simulation time 189717836 ps
CPU time 2.75 seconds
Started Apr 23 03:20:02 PM PDT 24
Finished Apr 23 03:20:05 PM PDT 24
Peak memory 217316 kb
Host smart-a7d9011d-670e-4491-b1d1-b327284d7e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150068018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1150068018
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1318841876
Short name T314
Test name
Test status
Simulation time 154253664 ps
CPU time 2.32 seconds
Started Apr 23 03:20:01 PM PDT 24
Finished Apr 23 03:20:04 PM PDT 24
Peak memory 219004 kb
Host smart-b698f2f9-b4e1-41a3-8052-4f4a394f3072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318841876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1318841876
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.678930519
Short name T455
Test name
Test status
Simulation time 3052499942 ps
CPU time 17.95 seconds
Started Apr 23 03:20:04 PM PDT 24
Finished Apr 23 03:20:22 PM PDT 24
Peak memory 222676 kb
Host smart-f93a61db-d8ff-4b21-83de-a401763b9597
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=678930519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.678930519
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3106658196
Short name T97
Test name
Test status
Simulation time 9931851448 ps
CPU time 56.89 seconds
Started Apr 23 03:19:57 PM PDT 24
Finished Apr 23 03:20:54 PM PDT 24
Peak memory 216876 kb
Host smart-9b08d776-4874-4708-9af8-39df835be24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106658196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3106658196
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1641362035
Short name T563
Test name
Test status
Simulation time 21835130020 ps
CPU time 12.56 seconds
Started Apr 23 03:19:56 PM PDT 24
Finished Apr 23 03:20:09 PM PDT 24
Peak memory 216896 kb
Host smart-ee55da73-0661-4533-9ce4-ead6f2f86c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641362035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1641362035
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3411833211
Short name T683
Test name
Test status
Simulation time 62081349 ps
CPU time 1.55 seconds
Started Apr 23 03:19:58 PM PDT 24
Finished Apr 23 03:20:00 PM PDT 24
Peak memory 216840 kb
Host smart-45e8e1db-6921-482c-b177-3097d697c4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411833211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3411833211
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2394107655
Short name T52
Test name
Test status
Simulation time 480671441 ps
CPU time 1.08 seconds
Started Apr 23 03:19:57 PM PDT 24
Finished Apr 23 03:19:59 PM PDT 24
Peak memory 207328 kb
Host smart-00571abf-9103-42ea-8451-777bf11e3097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394107655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2394107655
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4228099219
Short name T466
Test name
Test status
Simulation time 12821572 ps
CPU time 0.74 seconds
Started Apr 23 03:20:17 PM PDT 24
Finished Apr 23 03:20:18 PM PDT 24
Peak memory 206344 kb
Host smart-23cb1e65-6bcc-43ed-9237-c098a6d8b2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228099219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4228099219
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.625964005
Short name T492
Test name
Test status
Simulation time 131485743 ps
CPU time 0.79 seconds
Started Apr 23 03:20:07 PM PDT 24
Finished Apr 23 03:20:08 PM PDT 24
Peak memory 207188 kb
Host smart-3e733e66-f3c4-4662-8342-835ec85dfc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625964005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.625964005
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3473167798
Short name T643
Test name
Test status
Simulation time 578835859 ps
CPU time 17.01 seconds
Started Apr 23 03:20:12 PM PDT 24
Finished Apr 23 03:20:30 PM PDT 24
Peak memory 225044 kb
Host smart-ac7b5634-4115-4dfd-a3ae-037cec073671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473167798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3473167798
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1187260280
Short name T602
Test name
Test status
Simulation time 49650264510 ps
CPU time 95.82 seconds
Started Apr 23 03:20:07 PM PDT 24
Finished Apr 23 03:21:43 PM PDT 24
Peak memory 241448 kb
Host smart-cb2ecb36-e0e2-4b50-a0fc-f7d207f6bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187260280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1187260280
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.632917797
Short name T7
Test name
Test status
Simulation time 17406457905 ps
CPU time 16.26 seconds
Started Apr 23 03:20:12 PM PDT 24
Finished Apr 23 03:20:29 PM PDT 24
Peak memory 219876 kb
Host smart-79da3679-4c3a-4f41-807e-37d374718b15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=632917797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.632917797
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2252524092
Short name T484
Test name
Test status
Simulation time 1962715594 ps
CPU time 10.17 seconds
Started Apr 23 03:20:06 PM PDT 24
Finished Apr 23 03:20:17 PM PDT 24
Peak memory 216852 kb
Host smart-ed74f62e-64e3-411d-8244-c4a93f4f087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252524092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2252524092
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.688265204
Short name T53
Test name
Test status
Simulation time 171954844 ps
CPU time 2.28 seconds
Started Apr 23 03:20:09 PM PDT 24
Finished Apr 23 03:20:12 PM PDT 24
Peak memory 216804 kb
Host smart-c5f4bba9-6822-4220-8d29-262b9002f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688265204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.688265204
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1207639608
Short name T447
Test name
Test status
Simulation time 95006986 ps
CPU time 0.96 seconds
Started Apr 23 03:20:08 PM PDT 24
Finished Apr 23 03:20:10 PM PDT 24
Peak memory 206376 kb
Host smart-d9910d01-a4a0-42ba-aa74-bda1402bc8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207639608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1207639608
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2220473738
Short name T536
Test name
Test status
Simulation time 59471967708 ps
CPU time 39.42 seconds
Started Apr 23 03:20:10 PM PDT 24
Finished Apr 23 03:20:50 PM PDT 24
Peak memory 221640 kb
Host smart-985d6f31-fb62-483e-839a-8e9195e891f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220473738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2220473738
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2395852607
Short name T548
Test name
Test status
Simulation time 11120395 ps
CPU time 0.7 seconds
Started Apr 23 03:20:33 PM PDT 24
Finished Apr 23 03:20:35 PM PDT 24
Peak memory 205996 kb
Host smart-1801c051-4245-4ac7-8d5b-a96dc0b1f949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395852607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2395852607
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3242663287
Short name T708
Test name
Test status
Simulation time 27353038 ps
CPU time 0.77 seconds
Started Apr 23 03:20:18 PM PDT 24
Finished Apr 23 03:20:19 PM PDT 24
Peak memory 207148 kb
Host smart-7e12865b-2b3b-490d-855d-3410b1775294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242663287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3242663287
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4099720689
Short name T690
Test name
Test status
Simulation time 448346793 ps
CPU time 8.28 seconds
Started Apr 23 03:20:27 PM PDT 24
Finished Apr 23 03:20:35 PM PDT 24
Peak memory 233252 kb
Host smart-1ec44ae7-46ad-4e24-bf67-34ea3518ed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099720689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4099720689
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1869163770
Short name T532
Test name
Test status
Simulation time 127005476 ps
CPU time 2.36 seconds
Started Apr 23 03:20:24 PM PDT 24
Finished Apr 23 03:20:27 PM PDT 24
Peak memory 222968 kb
Host smart-eb327a48-0d19-4bb0-8c1a-1ce910025952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869163770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1869163770
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1912760924
Short name T581
Test name
Test status
Simulation time 8103165834 ps
CPU time 22.99 seconds
Started Apr 23 03:20:27 PM PDT 24
Finished Apr 23 03:20:51 PM PDT 24
Peak memory 219680 kb
Host smart-9715f02a-a9a2-40c7-ba5e-dc6e8ab5b474
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1912760924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1912760924
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3277692243
Short name T389
Test name
Test status
Simulation time 9159811330 ps
CPU time 19.86 seconds
Started Apr 23 03:20:18 PM PDT 24
Finished Apr 23 03:20:38 PM PDT 24
Peak memory 216940 kb
Host smart-b23840e1-c8f5-48b9-8be5-d4a24bba8df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277692243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3277692243
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.408134902
Short name T103
Test name
Test status
Simulation time 685554869 ps
CPU time 3.57 seconds
Started Apr 23 03:20:17 PM PDT 24
Finished Apr 23 03:20:21 PM PDT 24
Peak memory 216792 kb
Host smart-ca19fe92-50f0-4eb6-b3bb-c20cd1ff7fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408134902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.408134902
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.791629982
Short name T57
Test name
Test status
Simulation time 36946531 ps
CPU time 1.2 seconds
Started Apr 23 03:20:21 PM PDT 24
Finished Apr 23 03:20:23 PM PDT 24
Peak memory 216608 kb
Host smart-9d15a83a-672a-4afa-b1d9-680c036c6f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791629982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.791629982
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2188388840
Short name T462
Test name
Test status
Simulation time 75596867 ps
CPU time 0.92 seconds
Started Apr 23 03:20:22 PM PDT 24
Finished Apr 23 03:20:23 PM PDT 24
Peak memory 206316 kb
Host smart-ead09c48-69f7-45d9-9de1-0bb3253736b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188388840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2188388840
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.418531826
Short name T31
Test name
Test status
Simulation time 60084421 ps
CPU time 0.7 seconds
Started Apr 23 03:20:42 PM PDT 24
Finished Apr 23 03:20:43 PM PDT 24
Peak memory 206316 kb
Host smart-7dc590ca-5b70-4469-b96e-deca6b3e247d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418531826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.418531826
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2069635182
Short name T685
Test name
Test status
Simulation time 25577027 ps
CPU time 0.73 seconds
Started Apr 23 03:20:31 PM PDT 24
Finished Apr 23 03:20:32 PM PDT 24
Peak memory 206156 kb
Host smart-7facfeb2-5fc5-4b22-94c4-3c1d662c4137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069635182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2069635182
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.266566073
Short name T374
Test name
Test status
Simulation time 58746611707 ps
CPU time 150.4 seconds
Started Apr 23 03:20:40 PM PDT 24
Finished Apr 23 03:23:11 PM PDT 24
Peak memory 252872 kb
Host smart-e2c5c3a1-6960-489d-9e60-f6ef68c8d11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266566073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.266566073
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2381705591
Short name T114
Test name
Test status
Simulation time 2171161917 ps
CPU time 6.91 seconds
Started Apr 23 03:20:38 PM PDT 24
Finished Apr 23 03:20:46 PM PDT 24
Peak memory 221640 kb
Host smart-2c2ff7e3-e547-4714-8ade-8e307c884fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381705591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2381705591
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2621617855
Short name T327
Test name
Test status
Simulation time 9406526934 ps
CPU time 95.23 seconds
Started Apr 23 03:20:41 PM PDT 24
Finished Apr 23 03:22:16 PM PDT 24
Peak memory 221280 kb
Host smart-057f79da-7a83-4e02-9620-91a5cd813621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621617855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2621617855
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2175039080
Short name T450
Test name
Test status
Simulation time 795329005 ps
CPU time 3.93 seconds
Started Apr 23 03:20:37 PM PDT 24
Finished Apr 23 03:20:42 PM PDT 24
Peak memory 223352 kb
Host smart-3263652e-fb37-4731-a55c-ce9f0aad7f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175039080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2175039080
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2703066693
Short name T613
Test name
Test status
Simulation time 606578645 ps
CPU time 3.82 seconds
Started Apr 23 03:20:39 PM PDT 24
Finished Apr 23 03:20:43 PM PDT 24
Peak memory 219936 kb
Host smart-a0cbc512-b7b2-45e9-af79-c4df167289ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703066693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2703066693
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1625558011
Short name T381
Test name
Test status
Simulation time 6778427961 ps
CPU time 18.25 seconds
Started Apr 23 03:20:35 PM PDT 24
Finished Apr 23 03:20:53 PM PDT 24
Peak memory 217204 kb
Host smart-065b800c-5ffa-402d-8579-9c20f36783f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625558011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1625558011
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.642889807
Short name T595
Test name
Test status
Simulation time 3348368793 ps
CPU time 8.11 seconds
Started Apr 23 03:20:33 PM PDT 24
Finished Apr 23 03:20:41 PM PDT 24
Peak memory 216896 kb
Host smart-02538f34-dce6-4124-a559-2bb450b803f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642889807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.642889807
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3310293735
Short name T121
Test name
Test status
Simulation time 1109350285 ps
CPU time 3.79 seconds
Started Apr 23 03:20:34 PM PDT 24
Finished Apr 23 03:20:38 PM PDT 24
Peak memory 216892 kb
Host smart-abcf1869-25f3-4395-b5f1-d41a79a4aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310293735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3310293735
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2622832550
Short name T471
Test name
Test status
Simulation time 114543315 ps
CPU time 0.86 seconds
Started Apr 23 03:20:36 PM PDT 24
Finished Apr 23 03:20:38 PM PDT 24
Peak memory 207328 kb
Host smart-391671e0-ca89-4e7c-8d2a-790342ba772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622832550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2622832550
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3708592647
Short name T637
Test name
Test status
Simulation time 12516482 ps
CPU time 0.69 seconds
Started Apr 23 03:20:51 PM PDT 24
Finished Apr 23 03:20:52 PM PDT 24
Peak memory 205448 kb
Host smart-0e6ad245-4f2c-4ce9-b3a5-b03bdfe5cf68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708592647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3708592647
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1358521688
Short name T551
Test name
Test status
Simulation time 20185895 ps
CPU time 0.74 seconds
Started Apr 23 03:20:44 PM PDT 24
Finished Apr 23 03:20:45 PM PDT 24
Peak memory 206116 kb
Host smart-a5bfabc6-ce46-440a-a9d8-03aa1a5acf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358521688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1358521688
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2730492338
Short name T565
Test name
Test status
Simulation time 95644780745 ps
CPU time 73.47 seconds
Started Apr 23 03:20:45 PM PDT 24
Finished Apr 23 03:21:59 PM PDT 24
Peak memory 240204 kb
Host smart-16322b9c-776c-4209-9f9b-bcda74fd42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730492338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2730492338
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.886555061
Short name T636
Test name
Test status
Simulation time 5748566720 ps
CPU time 15.36 seconds
Started Apr 23 03:20:45 PM PDT 24
Finished Apr 23 03:21:01 PM PDT 24
Peak memory 224956 kb
Host smart-c4d0820d-11aa-459a-a105-cefde69fab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886555061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.886555061
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2761765623
Short name T190
Test name
Test status
Simulation time 1764955559 ps
CPU time 7.96 seconds
Started Apr 23 03:20:47 PM PDT 24
Finished Apr 23 03:20:55 PM PDT 24
Peak memory 233232 kb
Host smart-d7a0a3b8-140e-4be9-be56-cdf9f5f46f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761765623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2761765623
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3205854000
Short name T424
Test name
Test status
Simulation time 2595187517 ps
CPU time 5.06 seconds
Started Apr 23 03:20:44 PM PDT 24
Finished Apr 23 03:20:50 PM PDT 24
Peak memory 219400 kb
Host smart-ae43da4c-06a2-4db6-980d-c4d1644d202a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205854000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3205854000
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2376343062
Short name T583
Test name
Test status
Simulation time 2629401482 ps
CPU time 34.59 seconds
Started Apr 23 03:20:47 PM PDT 24
Finished Apr 23 03:21:22 PM PDT 24
Peak memory 216888 kb
Host smart-22bfa567-9cfe-4e94-9ed5-91c4bdd48140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376343062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2376343062
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3480071873
Short name T429
Test name
Test status
Simulation time 2442253697 ps
CPU time 8.14 seconds
Started Apr 23 03:20:44 PM PDT 24
Finished Apr 23 03:20:53 PM PDT 24
Peak memory 216880 kb
Host smart-83ea37a4-b0a2-4f02-ae51-f36b7efd88f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480071873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3480071873
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3461176054
Short name T396
Test name
Test status
Simulation time 506615502 ps
CPU time 2.57 seconds
Started Apr 23 03:20:41 PM PDT 24
Finished Apr 23 03:20:44 PM PDT 24
Peak memory 216868 kb
Host smart-6c3b63dd-463d-46bf-a378-b4c7616a07a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461176054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3461176054
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2835470833
Short name T641
Test name
Test status
Simulation time 40513962 ps
CPU time 0.73 seconds
Started Apr 23 03:20:41 PM PDT 24
Finished Apr 23 03:20:42 PM PDT 24
Peak memory 206368 kb
Host smart-952ecb71-3e35-4d98-b0e8-09c72f7e95bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835470833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2835470833
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2375348836
Short name T29
Test name
Test status
Simulation time 53009767 ps
CPU time 0.7 seconds
Started Apr 23 03:21:14 PM PDT 24
Finished Apr 23 03:21:15 PM PDT 24
Peak memory 205452 kb
Host smart-4c7881a1-bdb7-47f7-b99e-5c432502f453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375348836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2375348836
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3647932862
Short name T430
Test name
Test status
Simulation time 24600479 ps
CPU time 0.71 seconds
Started Apr 23 03:20:52 PM PDT 24
Finished Apr 23 03:20:53 PM PDT 24
Peak memory 206432 kb
Host smart-f0c419e1-db39-47e6-87e9-70a6bf0ba295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647932862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3647932862
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3405256745
Short name T702
Test name
Test status
Simulation time 2609003496 ps
CPU time 33.38 seconds
Started Apr 23 03:21:03 PM PDT 24
Finished Apr 23 03:21:37 PM PDT 24
Peak memory 249660 kb
Host smart-439bcbdf-1d4b-4590-8184-cafb4663aff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405256745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3405256745
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.228734244
Short name T338
Test name
Test status
Simulation time 938205829 ps
CPU time 5.92 seconds
Started Apr 23 03:21:00 PM PDT 24
Finished Apr 23 03:21:07 PM PDT 24
Peak memory 223140 kb
Host smart-f1621875-5962-4d68-810f-da50937aad61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228734244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.228734244
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.857506463
Short name T349
Test name
Test status
Simulation time 4477524638 ps
CPU time 12.56 seconds
Started Apr 23 03:21:03 PM PDT 24
Finished Apr 23 03:21:16 PM PDT 24
Peak memory 222836 kb
Host smart-54e59ab3-a2e8-4faa-b8fd-0efa4c201432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857506463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.857506463
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1458533464
Short name T193
Test name
Test status
Simulation time 7765541823 ps
CPU time 12.61 seconds
Started Apr 23 03:21:00 PM PDT 24
Finished Apr 23 03:21:13 PM PDT 24
Peak memory 218420 kb
Host smart-2abab471-a75c-4a50-93b3-d1b5557b1155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458533464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1458533464
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.85734464
Short name T550
Test name
Test status
Simulation time 801432811 ps
CPU time 5.83 seconds
Started Apr 23 03:21:05 PM PDT 24
Finished Apr 23 03:21:11 PM PDT 24
Peak memory 223556 kb
Host smart-e8356b51-3c4c-4ed0-920f-6276fc445a5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=85734464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direc
t.85734464
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.715820774
Short name T51
Test name
Test status
Simulation time 4992642411 ps
CPU time 28.19 seconds
Started Apr 23 03:20:52 PM PDT 24
Finished Apr 23 03:21:21 PM PDT 24
Peak memory 216952 kb
Host smart-86e1fdac-8ba1-4cd4-9306-d121fddf4d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715820774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.715820774
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2160952021
Short name T651
Test name
Test status
Simulation time 8849792794 ps
CPU time 25.6 seconds
Started Apr 23 03:20:53 PM PDT 24
Finished Apr 23 03:21:19 PM PDT 24
Peak memory 216932 kb
Host smart-1de83bd9-b5aa-4ada-97e8-0fb162dd3fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160952021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2160952021
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1638170703
Short name T709
Test name
Test status
Simulation time 91881150 ps
CPU time 1.15 seconds
Started Apr 23 03:20:54 PM PDT 24
Finished Apr 23 03:20:56 PM PDT 24
Peak memory 216832 kb
Host smart-11f812a9-8c4f-418b-b027-da76192633f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638170703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1638170703
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2476138201
Short name T566
Test name
Test status
Simulation time 68002422 ps
CPU time 0.89 seconds
Started Apr 23 03:20:55 PM PDT 24
Finished Apr 23 03:20:56 PM PDT 24
Peak memory 206352 kb
Host smart-18bd1a2e-980d-45cf-a693-4b7c34911116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476138201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2476138201
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1735875826
Short name T530
Test name
Test status
Simulation time 43631689 ps
CPU time 0.72 seconds
Started Apr 23 03:15:16 PM PDT 24
Finished Apr 23 03:15:17 PM PDT 24
Peak memory 205460 kb
Host smart-2aa0a4f9-30b2-4847-aee5-278d6add9ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735875826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
735875826
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1213184924
Short name T437
Test name
Test status
Simulation time 15030136 ps
CPU time 0.72 seconds
Started Apr 23 03:14:58 PM PDT 24
Finished Apr 23 03:14:59 PM PDT 24
Peak memory 206472 kb
Host smart-b4862495-b3a6-44b3-ab6d-f06f5773b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213184924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1213184924
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2604001153
Short name T677
Test name
Test status
Simulation time 428412152 ps
CPU time 7.63 seconds
Started Apr 23 03:15:08 PM PDT 24
Finished Apr 23 03:15:17 PM PDT 24
Peak memory 225052 kb
Host smart-162d01a8-0f04-4090-ac42-4c867dcb130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604001153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2604001153
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2212399810
Short name T65
Test name
Test status
Simulation time 1360614189 ps
CPU time 8.07 seconds
Started Apr 23 03:15:12 PM PDT 24
Finished Apr 23 03:15:20 PM PDT 24
Peak memory 226508 kb
Host smart-dc76aedc-d540-43c0-bf75-8af1f854bf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212399810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2212399810
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.148446156
Short name T477
Test name
Test status
Simulation time 1372972125 ps
CPU time 6.87 seconds
Started Apr 23 03:15:08 PM PDT 24
Finished Apr 23 03:15:16 PM PDT 24
Peak memory 222348 kb
Host smart-4acc77c6-a95c-44fe-aaf7-17375b89b3d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=148446156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.148446156
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.432808966
Short name T15
Test name
Test status
Simulation time 198916843 ps
CPU time 0.99 seconds
Started Apr 23 03:15:12 PM PDT 24
Finished Apr 23 03:15:14 PM PDT 24
Peak memory 235452 kb
Host smart-592f8d3c-3212-47e7-8d9b-cea5c5c3e9a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432808966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.432808966
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1785215726
Short name T100
Test name
Test status
Simulation time 5193190889 ps
CPU time 28.71 seconds
Started Apr 23 03:15:04 PM PDT 24
Finished Apr 23 03:15:33 PM PDT 24
Peak memory 216908 kb
Host smart-fa510aed-db48-4c62-9307-97d40a4abf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785215726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1785215726
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3790518641
Short name T546
Test name
Test status
Simulation time 1044686090 ps
CPU time 5.88 seconds
Started Apr 23 03:15:03 PM PDT 24
Finished Apr 23 03:15:09 PM PDT 24
Peak memory 216856 kb
Host smart-576d94b1-f222-462e-b126-564ac53d6a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790518641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3790518641
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3334389917
Short name T495
Test name
Test status
Simulation time 48994930 ps
CPU time 2.78 seconds
Started Apr 23 03:15:00 PM PDT 24
Finished Apr 23 03:15:03 PM PDT 24
Peak memory 208588 kb
Host smart-8c0ffa54-2563-4e64-bf45-604d33e24920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334389917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3334389917
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3731156686
Short name T615
Test name
Test status
Simulation time 426532401 ps
CPU time 0.95 seconds
Started Apr 23 03:15:13 PM PDT 24
Finished Apr 23 03:15:14 PM PDT 24
Peak memory 207404 kb
Host smart-fba29976-6113-4c01-9796-a82bf66dc26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731156686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3731156686
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3545230497
Short name T464
Test name
Test status
Simulation time 42824964 ps
CPU time 0.69 seconds
Started Apr 23 03:21:14 PM PDT 24
Finished Apr 23 03:21:16 PM PDT 24
Peak memory 206316 kb
Host smart-fc59878a-a632-480b-9ed7-15daac1a47dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545230497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3545230497
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.965032411
Short name T420
Test name
Test status
Simulation time 42349354 ps
CPU time 0.74 seconds
Started Apr 23 03:21:09 PM PDT 24
Finished Apr 23 03:21:10 PM PDT 24
Peak memory 206488 kb
Host smart-3584f89c-48f4-4ed1-b3e3-bd5b3da7fd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965032411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.965032411
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1372624561
Short name T473
Test name
Test status
Simulation time 3320807770 ps
CPU time 19.73 seconds
Started Apr 23 03:21:15 PM PDT 24
Finished Apr 23 03:21:35 PM PDT 24
Peak memory 233288 kb
Host smart-0f95a628-bcad-4145-a887-71b6216d0249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372624561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1372624561
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.988468751
Short name T571
Test name
Test status
Simulation time 9586575700 ps
CPU time 24.16 seconds
Started Apr 23 03:21:12 PM PDT 24
Finished Apr 23 03:21:36 PM PDT 24
Peak memory 217240 kb
Host smart-1dfea838-b4b6-4842-bdc2-d2e1dd366521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988468751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.988468751
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4283949220
Short name T353
Test name
Test status
Simulation time 421702804 ps
CPU time 9.32 seconds
Started Apr 23 03:21:10 PM PDT 24
Finished Apr 23 03:21:20 PM PDT 24
Peak memory 236356 kb
Host smart-d8b07248-be68-4773-9c61-7cee04e58f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283949220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4283949220
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.686242579
Short name T507
Test name
Test status
Simulation time 196972221 ps
CPU time 5.38 seconds
Started Apr 23 03:21:14 PM PDT 24
Finished Apr 23 03:21:20 PM PDT 24
Peak memory 220736 kb
Host smart-c917a30f-a676-44bb-b125-1f4e9c5d9dad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=686242579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.686242579
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1457462058
Short name T399
Test name
Test status
Simulation time 6953594345 ps
CPU time 28.46 seconds
Started Apr 23 03:21:07 PM PDT 24
Finished Apr 23 03:21:36 PM PDT 24
Peak memory 217200 kb
Host smart-cbbfd215-49bb-4b1c-9127-0e64697a1fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457462058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1457462058
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.566123823
Short name T517
Test name
Test status
Simulation time 2365754645 ps
CPU time 9.18 seconds
Started Apr 23 03:21:08 PM PDT 24
Finished Apr 23 03:21:18 PM PDT 24
Peak memory 216896 kb
Host smart-36240435-ea14-4da8-8d90-6f784bdbd7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566123823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.566123823
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3810711290
Short name T2
Test name
Test status
Simulation time 154284408 ps
CPU time 2.81 seconds
Started Apr 23 03:21:15 PM PDT 24
Finished Apr 23 03:21:18 PM PDT 24
Peak memory 216860 kb
Host smart-e0784c3c-8f7a-4a86-949a-489e7a7ce648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810711290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3810711290
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1375023221
Short name T474
Test name
Test status
Simulation time 20559178 ps
CPU time 0.72 seconds
Started Apr 23 03:21:12 PM PDT 24
Finished Apr 23 03:21:13 PM PDT 24
Peak memory 206324 kb
Host smart-aa4f9b04-b1bc-4d57-b572-9bec70811a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375023221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1375023221
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2289164136
Short name T440
Test name
Test status
Simulation time 21966130 ps
CPU time 0.69 seconds
Started Apr 23 03:21:24 PM PDT 24
Finished Apr 23 03:21:25 PM PDT 24
Peak memory 205432 kb
Host smart-b45950fd-80fd-4e7b-bb9e-5535803e453d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289164136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2289164136
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3238880990
Short name T209
Test name
Test status
Simulation time 444449857 ps
CPU time 6.5 seconds
Started Apr 23 03:21:21 PM PDT 24
Finished Apr 23 03:21:27 PM PDT 24
Peak memory 223824 kb
Host smart-b8b26c1f-f754-49fc-ac34-5dfc1214f1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238880990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3238880990
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.125564164
Short name T660
Test name
Test status
Simulation time 21373250 ps
CPU time 0.8 seconds
Started Apr 23 03:21:16 PM PDT 24
Finished Apr 23 03:21:17 PM PDT 24
Peak memory 207132 kb
Host smart-5524db6b-640a-4064-a065-54aeb9424363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125564164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.125564164
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.72015573
Short name T664
Test name
Test status
Simulation time 4974068994 ps
CPU time 34.04 seconds
Started Apr 23 03:21:24 PM PDT 24
Finished Apr 23 03:21:58 PM PDT 24
Peak memory 250680 kb
Host smart-98ef977b-b8ba-4b76-a026-1b3cab067fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72015573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.72015573
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1776680930
Short name T315
Test name
Test status
Simulation time 67981374194 ps
CPU time 45.48 seconds
Started Apr 23 03:21:25 PM PDT 24
Finished Apr 23 03:22:11 PM PDT 24
Peak memory 224012 kb
Host smart-b59d671b-2a90-4269-9f21-ebf190c4b57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776680930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1776680930
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.372271349
Short name T559
Test name
Test status
Simulation time 2619549366 ps
CPU time 10.86 seconds
Started Apr 23 03:21:25 PM PDT 24
Finished Apr 23 03:21:36 PM PDT 24
Peak memory 222584 kb
Host smart-4de3c067-7cb2-467b-ba1b-adf158d4fe93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=372271349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.372271349
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1209462180
Short name T661
Test name
Test status
Simulation time 2881159738 ps
CPU time 35.48 seconds
Started Apr 23 03:21:26 PM PDT 24
Finished Apr 23 03:22:01 PM PDT 24
Peak memory 216812 kb
Host smart-996db302-8af2-415d-9df2-18eb520f7837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209462180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1209462180
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2442771244
Short name T412
Test name
Test status
Simulation time 2201374648 ps
CPU time 8.35 seconds
Started Apr 23 03:21:19 PM PDT 24
Finished Apr 23 03:21:28 PM PDT 24
Peak memory 216904 kb
Host smart-2b5cab41-1e7c-4818-93dc-1c8c670adc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442771244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2442771244
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4265813284
Short name T633
Test name
Test status
Simulation time 463342262 ps
CPU time 2.31 seconds
Started Apr 23 03:21:18 PM PDT 24
Finished Apr 23 03:21:21 PM PDT 24
Peak memory 216840 kb
Host smart-42d1de9d-6b0f-43e1-bd56-027ce58be835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265813284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4265813284
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1200596652
Short name T547
Test name
Test status
Simulation time 155841590 ps
CPU time 1.13 seconds
Started Apr 23 03:21:25 PM PDT 24
Finished Apr 23 03:21:27 PM PDT 24
Peak memory 207316 kb
Host smart-ff7f6862-3906-497a-b4c2-ffe17c0b2058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200596652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1200596652
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.41257822
Short name T526
Test name
Test status
Simulation time 90446096 ps
CPU time 0.7 seconds
Started Apr 23 03:21:42 PM PDT 24
Finished Apr 23 03:21:43 PM PDT 24
Peak memory 206364 kb
Host smart-4c8b0927-a513-4c87-9e42-ae94b9d73121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.41257822
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1581723316
Short name T409
Test name
Test status
Simulation time 77465317 ps
CPU time 0.73 seconds
Started Apr 23 03:21:26 PM PDT 24
Finished Apr 23 03:21:27 PM PDT 24
Peak memory 206484 kb
Host smart-68cdc910-ee48-4015-8444-d0f4c4d3a0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581723316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1581723316
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1193128276
Short name T120
Test name
Test status
Simulation time 1303249616 ps
CPU time 23.4 seconds
Started Apr 23 03:21:38 PM PDT 24
Finished Apr 23 03:22:01 PM PDT 24
Peak memory 234776 kb
Host smart-759f2ba5-5ee1-4a6f-a75e-cfa0ba714551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193128276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1193128276
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.108539228
Short name T76
Test name
Test status
Simulation time 17961037402 ps
CPU time 14.84 seconds
Started Apr 23 03:21:39 PM PDT 24
Finished Apr 23 03:21:54 PM PDT 24
Peak memory 223376 kb
Host smart-c3ec1567-deac-4403-b395-1570e87cdbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108539228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.108539228
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4146996826
Short name T710
Test name
Test status
Simulation time 12411614435 ps
CPU time 13.92 seconds
Started Apr 23 03:21:34 PM PDT 24
Finished Apr 23 03:21:49 PM PDT 24
Peak memory 217432 kb
Host smart-e5031de9-092f-4017-aeaf-bb48e0851c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146996826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4146996826
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1126296512
Short name T704
Test name
Test status
Simulation time 860110800 ps
CPU time 5.41 seconds
Started Apr 23 03:21:38 PM PDT 24
Finished Apr 23 03:21:44 PM PDT 24
Peak memory 221880 kb
Host smart-ff7ede15-8b28-4321-b301-996938165335
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1126296512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1126296512
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2341253356
Short name T383
Test name
Test status
Simulation time 7857276701 ps
CPU time 33.09 seconds
Started Apr 23 03:21:29 PM PDT 24
Finished Apr 23 03:22:02 PM PDT 24
Peak memory 216844 kb
Host smart-4f0f43fc-3fd2-4587-b514-8bf21a805312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341253356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2341253356
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.347341108
Short name T415
Test name
Test status
Simulation time 740598121 ps
CPU time 3.87 seconds
Started Apr 23 03:21:33 PM PDT 24
Finished Apr 23 03:21:37 PM PDT 24
Peak memory 216864 kb
Host smart-4b30c221-27b8-48c5-91ff-2c591c375d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347341108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.347341108
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2779634171
Short name T533
Test name
Test status
Simulation time 135861155 ps
CPU time 0.92 seconds
Started Apr 23 03:21:31 PM PDT 24
Finished Apr 23 03:21:33 PM PDT 24
Peak memory 207744 kb
Host smart-f0f46430-fb9d-4e0d-af3a-828e0351f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779634171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2779634171
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.173535786
Short name T597
Test name
Test status
Simulation time 129642176 ps
CPU time 0.83 seconds
Started Apr 23 03:21:27 PM PDT 24
Finished Apr 23 03:21:29 PM PDT 24
Peak memory 206112 kb
Host smart-3bbaa0c1-3e08-425f-b462-6a55bc5d4e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173535786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.173535786
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1490372040
Short name T287
Test name
Test status
Simulation time 277897938 ps
CPU time 4.1 seconds
Started Apr 23 03:21:34 PM PDT 24
Finished Apr 23 03:21:38 PM PDT 24
Peak memory 225036 kb
Host smart-62268f0d-2ae1-4819-9bd8-20310e96030a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490372040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1490372040
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3566381354
Short name T427
Test name
Test status
Simulation time 19146767 ps
CPU time 0.71 seconds
Started Apr 23 03:21:53 PM PDT 24
Finished Apr 23 03:21:54 PM PDT 24
Peak memory 206068 kb
Host smart-c45825cd-3793-461c-aea5-f45be3446372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566381354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3566381354
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2761160638
Short name T458
Test name
Test status
Simulation time 17358868 ps
CPU time 0.73 seconds
Started Apr 23 03:21:44 PM PDT 24
Finished Apr 23 03:21:45 PM PDT 24
Peak memory 206164 kb
Host smart-379480b2-4574-4acb-987b-3c408fa56c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761160638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2761160638
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3699904120
Short name T82
Test name
Test status
Simulation time 1074516886 ps
CPU time 17.94 seconds
Started Apr 23 03:21:48 PM PDT 24
Finished Apr 23 03:22:07 PM PDT 24
Peak memory 233268 kb
Host smart-d12609a4-4d05-4a8a-a158-bfe512814dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699904120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3699904120
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3738896018
Short name T321
Test name
Test status
Simulation time 455858619 ps
CPU time 4.68 seconds
Started Apr 23 03:21:47 PM PDT 24
Finished Apr 23 03:21:53 PM PDT 24
Peak memory 219056 kb
Host smart-b43d361b-58b0-4309-809a-3e199e1da638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738896018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3738896018
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2736482037
Short name T333
Test name
Test status
Simulation time 6326477264 ps
CPU time 64.39 seconds
Started Apr 23 03:21:50 PM PDT 24
Finished Apr 23 03:22:55 PM PDT 24
Peak memory 241272 kb
Host smart-c2c302da-6b96-49f2-a304-9338a66fd4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736482037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2736482037
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4279258368
Short name T243
Test name
Test status
Simulation time 11313950334 ps
CPU time 8.56 seconds
Started Apr 23 03:21:49 PM PDT 24
Finished Apr 23 03:21:58 PM PDT 24
Peak memory 223348 kb
Host smart-c705429e-ec3b-4dab-9038-967229186a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279258368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4279258368
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.904156913
Short name T658
Test name
Test status
Simulation time 837897468 ps
CPU time 4.1 seconds
Started Apr 23 03:21:53 PM PDT 24
Finished Apr 23 03:21:58 PM PDT 24
Peak memory 222496 kb
Host smart-d987031b-28de-4f02-91f0-4fb6066f909b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=904156913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.904156913
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4158390495
Short name T556
Test name
Test status
Simulation time 51191529549 ps
CPU time 55.74 seconds
Started Apr 23 03:21:46 PM PDT 24
Finished Apr 23 03:22:42 PM PDT 24
Peak memory 216920 kb
Host smart-2ef18bd5-ca5e-42aa-80e4-c5f0e9ffa2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158390495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4158390495
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3262300961
Short name T102
Test name
Test status
Simulation time 22227466633 ps
CPU time 22.24 seconds
Started Apr 23 03:21:45 PM PDT 24
Finished Apr 23 03:22:08 PM PDT 24
Peak memory 216828 kb
Host smart-9b971e0b-cfc7-4706-9a73-9e8b9d14fdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262300961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3262300961
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1141817481
Short name T397
Test name
Test status
Simulation time 57228653 ps
CPU time 0.87 seconds
Started Apr 23 03:21:44 PM PDT 24
Finished Apr 23 03:21:45 PM PDT 24
Peak memory 206836 kb
Host smart-6422de07-5152-43d0-8507-f291fca3e7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141817481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1141817481
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.301889597
Short name T670
Test name
Test status
Simulation time 43642662 ps
CPU time 0.95 seconds
Started Apr 23 03:21:45 PM PDT 24
Finished Apr 23 03:21:47 PM PDT 24
Peak memory 207380 kb
Host smart-bb1a6f24-be28-4db7-be4b-8330362b9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301889597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.301889597
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.814877425
Short name T318
Test name
Test status
Simulation time 876895257 ps
CPU time 3.26 seconds
Started Apr 23 03:21:47 PM PDT 24
Finished Apr 23 03:21:51 PM PDT 24
Peak memory 223808 kb
Host smart-b64a47db-f80e-4d35-8c23-206ca8661dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814877425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.814877425
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3200918641
Short name T509
Test name
Test status
Simulation time 25172347 ps
CPU time 0.74 seconds
Started Apr 23 03:22:01 PM PDT 24
Finished Apr 23 03:22:02 PM PDT 24
Peak memory 206020 kb
Host smart-52d38a9e-f1be-4947-8db8-e8b33f3b9d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200918641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3200918641
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3885954823
Short name T266
Test name
Test status
Simulation time 38453360 ps
CPU time 2.74 seconds
Started Apr 23 03:21:59 PM PDT 24
Finished Apr 23 03:22:03 PM PDT 24
Peak memory 222828 kb
Host smart-088b325a-50a4-460d-8b7a-e24e88b9cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885954823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3885954823
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1554919451
Short name T468
Test name
Test status
Simulation time 55358384 ps
CPU time 0.8 seconds
Started Apr 23 03:21:51 PM PDT 24
Finished Apr 23 03:21:53 PM PDT 24
Peak memory 207136 kb
Host smart-b703d9b4-c8f3-45bd-a36a-c0bf62fe42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554919451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1554919451
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3547475836
Short name T292
Test name
Test status
Simulation time 2355103189 ps
CPU time 35.91 seconds
Started Apr 23 03:21:58 PM PDT 24
Finished Apr 23 03:22:35 PM PDT 24
Peak memory 241520 kb
Host smart-d94f16fb-c9f6-47bd-981b-9cbd9fa7af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547475836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3547475836
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1095865345
Short name T258
Test name
Test status
Simulation time 1321090458 ps
CPU time 7.55 seconds
Started Apr 23 03:21:59 PM PDT 24
Finished Apr 23 03:22:07 PM PDT 24
Peak memory 219372 kb
Host smart-88fee106-5a07-456e-9664-9f88c373c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095865345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1095865345
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.311417405
Short name T184
Test name
Test status
Simulation time 1379266008 ps
CPU time 19.95 seconds
Started Apr 23 03:21:59 PM PDT 24
Finished Apr 23 03:22:19 PM PDT 24
Peak memory 224164 kb
Host smart-4ae9066c-2a79-4133-b5ee-ed5436aeca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311417405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.311417405
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1688521583
Short name T62
Test name
Test status
Simulation time 5657008556 ps
CPU time 16.43 seconds
Started Apr 23 03:21:56 PM PDT 24
Finished Apr 23 03:22:13 PM PDT 24
Peak memory 240932 kb
Host smart-6614e82a-a482-4c2e-9b44-db787821d16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688521583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1688521583
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2827133044
Short name T218
Test name
Test status
Simulation time 1370709331 ps
CPU time 6.17 seconds
Started Apr 23 03:21:55 PM PDT 24
Finished Apr 23 03:22:02 PM PDT 24
Peak memory 219048 kb
Host smart-b2516046-e7c6-49c8-8d3e-afec9dd2b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827133044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2827133044
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1105814819
Short name T711
Test name
Test status
Simulation time 183711525 ps
CPU time 4.59 seconds
Started Apr 23 03:21:58 PM PDT 24
Finished Apr 23 03:22:03 PM PDT 24
Peak memory 222956 kb
Host smart-234031a5-2ae0-4c5d-9d4b-f683d0ca1850
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1105814819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1105814819
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3735480492
Short name T394
Test name
Test status
Simulation time 8555732700 ps
CPU time 41.69 seconds
Started Apr 23 03:21:53 PM PDT 24
Finished Apr 23 03:22:35 PM PDT 24
Peak memory 216952 kb
Host smart-fb114745-e042-4a12-96e2-079595f0e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735480492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3735480492
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3468917750
Short name T445
Test name
Test status
Simulation time 762912225 ps
CPU time 4.99 seconds
Started Apr 23 03:21:51 PM PDT 24
Finished Apr 23 03:21:56 PM PDT 24
Peak memory 216808 kb
Host smart-4a890650-0e78-42eb-893a-870085d45db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468917750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3468917750
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.569360909
Short name T453
Test name
Test status
Simulation time 102036253 ps
CPU time 1 seconds
Started Apr 23 03:21:54 PM PDT 24
Finished Apr 23 03:21:56 PM PDT 24
Peak memory 207672 kb
Host smart-6b2fa0fe-aaa7-4bac-a241-9c548cc34b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569360909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.569360909
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2152761601
Short name T598
Test name
Test status
Simulation time 188433358 ps
CPU time 1.16 seconds
Started Apr 23 03:21:52 PM PDT 24
Finished Apr 23 03:21:53 PM PDT 24
Peak memory 207344 kb
Host smart-1e9aa818-596e-4190-9bfb-8570b4dd5780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152761601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2152761601
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3777105455
Short name T313
Test name
Test status
Simulation time 32848847462 ps
CPU time 9.1 seconds
Started Apr 23 03:21:58 PM PDT 24
Finished Apr 23 03:22:09 PM PDT 24
Peak memory 225072 kb
Host smart-c8a344ac-404c-4b65-8089-e599328edb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777105455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3777105455
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2570365800
Short name T454
Test name
Test status
Simulation time 20170229 ps
CPU time 0.72 seconds
Started Apr 23 03:22:14 PM PDT 24
Finished Apr 23 03:22:15 PM PDT 24
Peak memory 205444 kb
Host smart-60cc898a-87a8-4e5a-8ef3-b94b8200e296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570365800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2570365800
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.112341808
Short name T668
Test name
Test status
Simulation time 21008306 ps
CPU time 0.79 seconds
Started Apr 23 03:22:04 PM PDT 24
Finished Apr 23 03:22:05 PM PDT 24
Peak memory 207168 kb
Host smart-6a46813a-3cb0-4d8f-99e8-a99a792cad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112341808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.112341808
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3525652196
Short name T305
Test name
Test status
Simulation time 442608117 ps
CPU time 16.14 seconds
Started Apr 23 03:22:09 PM PDT 24
Finished Apr 23 03:22:26 PM PDT 24
Peak memory 249608 kb
Host smart-1cab1a03-aac4-4ec8-921b-76cab162a351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525652196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3525652196
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2713165826
Short name T230
Test name
Test status
Simulation time 1220657047 ps
CPU time 6.59 seconds
Started Apr 23 03:22:11 PM PDT 24
Finished Apr 23 03:22:18 PM PDT 24
Peak memory 233036 kb
Host smart-c2e5ec19-b336-4f28-99a9-5e1e33aece54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713165826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2713165826
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1318383200
Short name T249
Test name
Test status
Simulation time 8955677597 ps
CPU time 8.97 seconds
Started Apr 23 03:22:07 PM PDT 24
Finished Apr 23 03:22:17 PM PDT 24
Peak memory 220840 kb
Host smart-2a51687c-fd88-4617-b793-fb8922a3e210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318383200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1318383200
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3388338406
Short name T631
Test name
Test status
Simulation time 2810345462 ps
CPU time 16.36 seconds
Started Apr 23 03:22:12 PM PDT 24
Finished Apr 23 03:22:28 PM PDT 24
Peak memory 221160 kb
Host smart-f1c869a7-912f-4d58-8a13-a088a7404d4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388338406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3388338406
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4070414545
Short name T181
Test name
Test status
Simulation time 6558090121 ps
CPU time 22.36 seconds
Started Apr 23 03:22:07 PM PDT 24
Finished Apr 23 03:22:30 PM PDT 24
Peak memory 216884 kb
Host smart-9f125d80-0fde-4c44-8a9f-c25663a2ae5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070414545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4070414545
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3029974623
Short name T537
Test name
Test status
Simulation time 3040238542 ps
CPU time 7.74 seconds
Started Apr 23 03:22:07 PM PDT 24
Finished Apr 23 03:22:15 PM PDT 24
Peak memory 216872 kb
Host smart-e1d44c2f-4996-45be-bfea-2d05a24920c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029974623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3029974623
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.707228347
Short name T679
Test name
Test status
Simulation time 190982111 ps
CPU time 1.7 seconds
Started Apr 23 03:22:08 PM PDT 24
Finished Apr 23 03:22:10 PM PDT 24
Peak memory 208652 kb
Host smart-f14da2d6-acca-47e1-8171-4c173c558f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707228347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.707228347
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2616282356
Short name T542
Test name
Test status
Simulation time 92018569 ps
CPU time 0.77 seconds
Started Apr 23 03:22:06 PM PDT 24
Finished Apr 23 03:22:07 PM PDT 24
Peak memory 206328 kb
Host smart-56741aa1-25a0-408c-8a4e-b1a8adf95ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616282356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2616282356
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.563001457
Short name T248
Test name
Test status
Simulation time 615342052 ps
CPU time 9.24 seconds
Started Apr 23 03:22:09 PM PDT 24
Finished Apr 23 03:22:19 PM PDT 24
Peak memory 240280 kb
Host smart-6e86d378-f604-4aaa-b264-0d4d1cc795c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563001457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.563001457
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2258824307
Short name T419
Test name
Test status
Simulation time 20117793 ps
CPU time 0.73 seconds
Started Apr 23 03:22:25 PM PDT 24
Finished Apr 23 03:22:28 PM PDT 24
Peak memory 205452 kb
Host smart-af2a64cc-d684-4a65-bb00-c2d46918b10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258824307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2258824307
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.986286375
Short name T645
Test name
Test status
Simulation time 17036561 ps
CPU time 0.72 seconds
Started Apr 23 03:22:17 PM PDT 24
Finished Apr 23 03:22:18 PM PDT 24
Peak memory 206480 kb
Host smart-bc5cca40-a99c-48d2-a8c7-a632757a9978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986286375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.986286375
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1168082862
Short name T481
Test name
Test status
Simulation time 30283995321 ps
CPU time 85.36 seconds
Started Apr 23 03:22:21 PM PDT 24
Finished Apr 23 03:23:47 PM PDT 24
Peak memory 241424 kb
Host smart-69814d4d-0d05-4189-b108-02d3055070eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168082862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1168082862
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.107148450
Short name T421
Test name
Test status
Simulation time 112284494 ps
CPU time 3.03 seconds
Started Apr 23 03:22:19 PM PDT 24
Finished Apr 23 03:22:22 PM PDT 24
Peak memory 219512 kb
Host smart-92b8cad1-fb51-420e-9b02-91aa1502dec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107148450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.107148450
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2479191102
Short name T77
Test name
Test status
Simulation time 301905546 ps
CPU time 4.82 seconds
Started Apr 23 03:22:17 PM PDT 24
Finished Apr 23 03:22:22 PM PDT 24
Peak memory 222740 kb
Host smart-7e31ef71-2e23-4b76-9a68-03f868252670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479191102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2479191102
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2840144952
Short name T596
Test name
Test status
Simulation time 1453454719 ps
CPU time 13.75 seconds
Started Apr 23 03:22:21 PM PDT 24
Finished Apr 23 03:22:36 PM PDT 24
Peak memory 221048 kb
Host smart-c0b1fd38-56fc-4e7a-9087-12607f0530bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2840144952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2840144952
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2681733469
Short name T589
Test name
Test status
Simulation time 10033826381 ps
CPU time 59.44 seconds
Started Apr 23 03:22:14 PM PDT 24
Finished Apr 23 03:23:14 PM PDT 24
Peak memory 216956 kb
Host smart-c0f44be9-48a2-4c7d-bf5b-d6f1890ad9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681733469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2681733469
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2891962458
Short name T549
Test name
Test status
Simulation time 7827356155 ps
CPU time 16.26 seconds
Started Apr 23 03:22:14 PM PDT 24
Finished Apr 23 03:22:31 PM PDT 24
Peak memory 216940 kb
Host smart-ae24635f-9bec-40a3-89e4-4b18b2dd7804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891962458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2891962458
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3766853628
Short name T402
Test name
Test status
Simulation time 310533470 ps
CPU time 3.41 seconds
Started Apr 23 03:22:17 PM PDT 24
Finished Apr 23 03:22:21 PM PDT 24
Peak memory 216864 kb
Host smart-ed315985-e3db-4139-94ea-220fe6f588e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766853628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3766853628
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1225490323
Short name T487
Test name
Test status
Simulation time 141807966 ps
CPU time 0.82 seconds
Started Apr 23 03:22:14 PM PDT 24
Finished Apr 23 03:22:16 PM PDT 24
Peak memory 206264 kb
Host smart-25393b87-4298-4279-85a8-425578ac69dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225490323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1225490323
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.68308278
Short name T674
Test name
Test status
Simulation time 34894634 ps
CPU time 0.7 seconds
Started Apr 23 03:22:35 PM PDT 24
Finished Apr 23 03:22:36 PM PDT 24
Peak memory 206052 kb
Host smart-36bb19bc-d97f-4073-bed4-be515b5b5100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68308278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.68308278
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3622800260
Short name T552
Test name
Test status
Simulation time 49981089 ps
CPU time 0.75 seconds
Started Apr 23 03:22:23 PM PDT 24
Finished Apr 23 03:22:25 PM PDT 24
Peak memory 206124 kb
Host smart-e9eba65f-12a3-4c20-886f-63242c4f5973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622800260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3622800260
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1876122592
Short name T308
Test name
Test status
Simulation time 14507072606 ps
CPU time 25.78 seconds
Started Apr 23 03:22:34 PM PDT 24
Finished Apr 23 03:23:00 PM PDT 24
Peak memory 225064 kb
Host smart-a78b44ec-9a79-4eec-b66d-86b9770e9f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876122592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1876122592
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1644315487
Short name T228
Test name
Test status
Simulation time 9938358476 ps
CPU time 28.45 seconds
Started Apr 23 03:22:32 PM PDT 24
Finished Apr 23 03:23:00 PM PDT 24
Peak memory 234640 kb
Host smart-42cd946d-83a5-488c-8c81-6a2e073c9dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644315487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1644315487
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1692414281
Short name T158
Test name
Test status
Simulation time 89331146 ps
CPU time 3.67 seconds
Started Apr 23 03:22:33 PM PDT 24
Finished Apr 23 03:22:37 PM PDT 24
Peak memory 222988 kb
Host smart-5f1c6a7a-4e47-4275-a3e1-1126bc0212c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692414281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1692414281
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1674320378
Short name T388
Test name
Test status
Simulation time 7351069342 ps
CPU time 30.14 seconds
Started Apr 23 03:22:32 PM PDT 24
Finished Apr 23 03:23:02 PM PDT 24
Peak memory 216880 kb
Host smart-3be102c2-466d-4466-8d28-21b1daa813da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674320378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1674320378
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3824225799
Short name T520
Test name
Test status
Simulation time 40572676341 ps
CPU time 30.81 seconds
Started Apr 23 03:22:25 PM PDT 24
Finished Apr 23 03:22:57 PM PDT 24
Peak memory 217968 kb
Host smart-d2ca5a08-f4c7-4b5b-9ab0-ee8546f6198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824225799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3824225799
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1144961998
Short name T604
Test name
Test status
Simulation time 203306540 ps
CPU time 1.51 seconds
Started Apr 23 03:22:30 PM PDT 24
Finished Apr 23 03:22:32 PM PDT 24
Peak memory 208668 kb
Host smart-a5f125a0-c24e-43e4-a667-454dd1270d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144961998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1144961998
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1393455724
Short name T459
Test name
Test status
Simulation time 97967291 ps
CPU time 0.8 seconds
Started Apr 23 03:22:28 PM PDT 24
Finished Apr 23 03:22:30 PM PDT 24
Peak memory 206372 kb
Host smart-b1566600-ca8f-4e7a-bf8a-f464f967f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393455724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1393455724
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.973170798
Short name T590
Test name
Test status
Simulation time 32673681 ps
CPU time 0.71 seconds
Started Apr 23 03:22:45 PM PDT 24
Finished Apr 23 03:22:46 PM PDT 24
Peak memory 206320 kb
Host smart-eb856654-9d51-40cf-a8a6-9b90528e1c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973170798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.973170798
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4081381381
Short name T573
Test name
Test status
Simulation time 42284937 ps
CPU time 0.73 seconds
Started Apr 23 03:22:36 PM PDT 24
Finished Apr 23 03:22:37 PM PDT 24
Peak memory 207444 kb
Host smart-8a9d0dc4-c6ea-4f2d-ba75-399b6917f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081381381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4081381381
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2823216824
Short name T302
Test name
Test status
Simulation time 694120212 ps
CPU time 14.54 seconds
Started Apr 23 03:22:45 PM PDT 24
Finished Apr 23 03:23:00 PM PDT 24
Peak memory 233240 kb
Host smart-1bde6b74-71a7-44e0-a452-b07c4556af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823216824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2823216824
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3335547196
Short name T687
Test name
Test status
Simulation time 805574017 ps
CPU time 3.92 seconds
Started Apr 23 03:22:41 PM PDT 24
Finished Apr 23 03:22:45 PM PDT 24
Peak memory 220856 kb
Host smart-55f1611a-8b49-4d39-9e0c-343116ab1b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335547196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3335547196
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1524780814
Short name T469
Test name
Test status
Simulation time 1413211784 ps
CPU time 3.16 seconds
Started Apr 23 03:22:41 PM PDT 24
Finished Apr 23 03:22:45 PM PDT 24
Peak memory 218916 kb
Host smart-e5a14ea2-0541-4dd3-bc56-89a74bc4f4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524780814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1524780814
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2432581740
Short name T237
Test name
Test status
Simulation time 576713424 ps
CPU time 4.53 seconds
Started Apr 23 03:22:40 PM PDT 24
Finished Apr 23 03:22:45 PM PDT 24
Peak memory 233012 kb
Host smart-29db89bf-533e-4596-9a35-71f1d474ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432581740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2432581740
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3185537648
Short name T672
Test name
Test status
Simulation time 1306647256 ps
CPU time 8.46 seconds
Started Apr 23 03:22:45 PM PDT 24
Finished Apr 23 03:22:54 PM PDT 24
Peak memory 223508 kb
Host smart-9f146906-efa3-4b07-8661-5217928a397a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3185537648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3185537648
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.110015704
Short name T627
Test name
Test status
Simulation time 8282862149 ps
CPU time 48.31 seconds
Started Apr 23 03:22:36 PM PDT 24
Finished Apr 23 03:23:25 PM PDT 24
Peak memory 216832 kb
Host smart-85f8e31b-7274-42a8-89ae-474b6d17c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110015704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.110015704
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1584277835
Short name T634
Test name
Test status
Simulation time 1923784391 ps
CPU time 3.07 seconds
Started Apr 23 03:22:37 PM PDT 24
Finished Apr 23 03:22:40 PM PDT 24
Peak memory 216796 kb
Host smart-411f3740-1be5-49e9-aebb-ced5aba73b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584277835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1584277835
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2444387667
Short name T523
Test name
Test status
Simulation time 607930837 ps
CPU time 2.98 seconds
Started Apr 23 03:22:40 PM PDT 24
Finished Apr 23 03:22:44 PM PDT 24
Peak memory 216856 kb
Host smart-9672fc10-9701-4d68-8340-c4012485bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444387667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2444387667
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3901680569
Short name T436
Test name
Test status
Simulation time 170914278 ps
CPU time 0.84 seconds
Started Apr 23 03:22:42 PM PDT 24
Finished Apr 23 03:22:43 PM PDT 24
Peak memory 206340 kb
Host smart-ce443845-4261-4ad9-8f66-29f8825e4103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901680569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3901680569
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1491891377
Short name T235
Test name
Test status
Simulation time 47997765112 ps
CPU time 37.53 seconds
Started Apr 23 03:22:46 PM PDT 24
Finished Apr 23 03:23:24 PM PDT 24
Peak memory 223012 kb
Host smart-83ec6b41-2e9f-4abd-bd79-24881c02de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491891377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1491891377
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1945631011
Short name T671
Test name
Test status
Simulation time 50197344 ps
CPU time 0.72 seconds
Started Apr 23 03:22:58 PM PDT 24
Finished Apr 23 03:22:59 PM PDT 24
Peak memory 206048 kb
Host smart-7d5c0589-3c63-49c0-ae35-e227aeaa8e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945631011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1945631011
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1815705109
Short name T446
Test name
Test status
Simulation time 15869645 ps
CPU time 0.76 seconds
Started Apr 23 03:22:46 PM PDT 24
Finished Apr 23 03:22:47 PM PDT 24
Peak memory 207124 kb
Host smart-3390e2e5-3034-4121-950f-44cadf971d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815705109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1815705109
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.371586177
Short name T297
Test name
Test status
Simulation time 7888659857 ps
CPU time 34.67 seconds
Started Apr 23 03:22:55 PM PDT 24
Finished Apr 23 03:23:30 PM PDT 24
Peak memory 251616 kb
Host smart-bb764e8e-d654-466c-97e4-d199d83c9002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371586177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.371586177
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3189847949
Short name T260
Test name
Test status
Simulation time 1384175736 ps
CPU time 13.66 seconds
Started Apr 23 03:22:51 PM PDT 24
Finished Apr 23 03:23:05 PM PDT 24
Peak memory 219328 kb
Host smart-02d7479c-e463-483c-b8fa-9397a91bee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189847949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3189847949
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3457220494
Short name T200
Test name
Test status
Simulation time 293990193 ps
CPU time 3.81 seconds
Started Apr 23 03:22:51 PM PDT 24
Finished Apr 23 03:22:55 PM PDT 24
Peak memory 218872 kb
Host smart-e7c48d7a-3d0d-4778-8a61-0526d9081304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457220494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3457220494
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.692567476
Short name T470
Test name
Test status
Simulation time 564944620 ps
CPU time 4.43 seconds
Started Apr 23 03:22:56 PM PDT 24
Finished Apr 23 03:23:01 PM PDT 24
Peak memory 219648 kb
Host smart-385d098d-7dd8-4eda-a7f3-58dd9ec37ba3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=692567476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.692567476
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1090052245
Short name T400
Test name
Test status
Simulation time 7855885069 ps
CPU time 33.13 seconds
Started Apr 23 03:22:48 PM PDT 24
Finished Apr 23 03:23:22 PM PDT 24
Peak memory 216884 kb
Host smart-f46986e2-8c2f-493d-b749-9ccc39dd597d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090052245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1090052245
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.384521781
Short name T441
Test name
Test status
Simulation time 14120051467 ps
CPU time 12.79 seconds
Started Apr 23 03:22:48 PM PDT 24
Finished Apr 23 03:23:01 PM PDT 24
Peak memory 216944 kb
Host smart-210df48a-088d-4a61-8993-366c995cf731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384521781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.384521781
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3520013982
Short name T561
Test name
Test status
Simulation time 563859786 ps
CPU time 9.2 seconds
Started Apr 23 03:22:47 PM PDT 24
Finished Apr 23 03:22:57 PM PDT 24
Peak memory 216864 kb
Host smart-20372e8b-88fc-4960-9076-fd0ec0ced071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520013982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3520013982
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2020089075
Short name T493
Test name
Test status
Simulation time 556339375 ps
CPU time 1.11 seconds
Started Apr 23 03:22:49 PM PDT 24
Finished Apr 23 03:22:51 PM PDT 24
Peak memory 207316 kb
Host smart-fcac6f09-4e55-4b57-aae7-256284217e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020089075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2020089075
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1677409564
Short name T574
Test name
Test status
Simulation time 14084009 ps
CPU time 0.73 seconds
Started Apr 23 03:15:28 PM PDT 24
Finished Apr 23 03:15:29 PM PDT 24
Peak memory 206044 kb
Host smart-330806a5-1eba-401f-bd93-3cf8ac739131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677409564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
677409564
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2944964279
Short name T650
Test name
Test status
Simulation time 25395541 ps
CPU time 0.77 seconds
Started Apr 23 03:15:14 PM PDT 24
Finished Apr 23 03:15:15 PM PDT 24
Peak memory 206160 kb
Host smart-74e99e5e-b189-4fd9-9e61-cce6c565d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944964279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2944964279
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4052499391
Short name T280
Test name
Test status
Simulation time 1027059016 ps
CPU time 17.53 seconds
Started Apr 23 03:15:21 PM PDT 24
Finished Apr 23 03:15:39 PM PDT 24
Peak memory 220440 kb
Host smart-d7826501-1d3d-4794-af3d-93d4817193c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052499391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4052499391
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.314070612
Short name T188
Test name
Test status
Simulation time 2247386201 ps
CPU time 4.63 seconds
Started Apr 23 03:15:20 PM PDT 24
Finished Apr 23 03:15:24 PM PDT 24
Peak memory 219728 kb
Host smart-da16a347-5a44-4f1f-8050-0d264db33989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314070612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
314070612
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1423486921
Short name T75
Test name
Test status
Simulation time 157623374 ps
CPU time 4.62 seconds
Started Apr 23 03:15:27 PM PDT 24
Finished Apr 23 03:15:31 PM PDT 24
Peak memory 223572 kb
Host smart-e5a2a811-d162-4bc7-9ed9-9e7977db260b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423486921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1423486921
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1692008574
Short name T32
Test name
Test status
Simulation time 148858314 ps
CPU time 1.01 seconds
Started Apr 23 03:15:32 PM PDT 24
Finished Apr 23 03:15:34 PM PDT 24
Peak memory 235412 kb
Host smart-c5e9c786-29aa-47ca-a611-f92812ed9a2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692008574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1692008574
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3306640810
Short name T714
Test name
Test status
Simulation time 4990473849 ps
CPU time 21.21 seconds
Started Apr 23 03:15:17 PM PDT 24
Finished Apr 23 03:15:39 PM PDT 24
Peak memory 220532 kb
Host smart-08e4b9d5-9390-4e43-99e3-707a30a7bc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306640810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3306640810
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2204444006
Short name T444
Test name
Test status
Simulation time 5095509128 ps
CPU time 9.05 seconds
Started Apr 23 03:15:15 PM PDT 24
Finished Apr 23 03:15:25 PM PDT 24
Peak memory 216940 kb
Host smart-1812e4b3-7a31-4f7f-ac15-acbfa903c1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204444006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2204444006
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.362252769
Short name T499
Test name
Test status
Simulation time 140605276 ps
CPU time 2.12 seconds
Started Apr 23 03:15:16 PM PDT 24
Finished Apr 23 03:15:19 PM PDT 24
Peak memory 216984 kb
Host smart-7749e421-8ed5-4b43-8cbc-8c90fc1d0d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362252769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.362252769
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.468349418
Short name T572
Test name
Test status
Simulation time 53116582 ps
CPU time 0.89 seconds
Started Apr 23 03:15:16 PM PDT 24
Finished Apr 23 03:15:17 PM PDT 24
Peak memory 206312 kb
Host smart-e9465eb0-cc00-4adf-bafc-03b3af23eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468349418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.468349418
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1307829056
Short name T680
Test name
Test status
Simulation time 12743443 ps
CPU time 0.73 seconds
Started Apr 23 03:23:12 PM PDT 24
Finished Apr 23 03:23:13 PM PDT 24
Peak memory 205988 kb
Host smart-8f64e271-0310-4706-aeb9-d2ea60db1d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307829056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1307829056
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.552222796
Short name T282
Test name
Test status
Simulation time 590940441 ps
CPU time 2.11 seconds
Started Apr 23 03:23:09 PM PDT 24
Finished Apr 23 03:23:11 PM PDT 24
Peak memory 219536 kb
Host smart-2e3ef5c2-601c-4200-9e4d-a0e367134f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552222796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.552222796
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1587369393
Short name T16
Test name
Test status
Simulation time 26405625 ps
CPU time 0.73 seconds
Started Apr 23 03:22:57 PM PDT 24
Finished Apr 23 03:22:59 PM PDT 24
Peak memory 206168 kb
Host smart-62c8119e-5873-411e-9fb9-d1e0560eb625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587369393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1587369393
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.482411328
Short name T648
Test name
Test status
Simulation time 1426312025 ps
CPU time 12.03 seconds
Started Apr 23 03:23:09 PM PDT 24
Finished Apr 23 03:23:21 PM PDT 24
Peak memory 241440 kb
Host smart-937d8217-00cd-4ef7-a8e4-8119c42c95df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482411328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.482411328
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3851376315
Short name T343
Test name
Test status
Simulation time 761580146 ps
CPU time 3.24 seconds
Started Apr 23 03:23:04 PM PDT 24
Finished Apr 23 03:23:08 PM PDT 24
Peak memory 223256 kb
Host smart-d9f6bceb-3d61-4587-a0d8-4c6196595044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851376315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3851376315
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.980660975
Short name T669
Test name
Test status
Simulation time 4583644709 ps
CPU time 6.89 seconds
Started Apr 23 03:23:07 PM PDT 24
Finished Apr 23 03:23:15 PM PDT 24
Peak memory 223648 kb
Host smart-1c7e6937-a26a-4703-8672-148e74cb9325
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=980660975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.980660975
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.423342027
Short name T391
Test name
Test status
Simulation time 7536301992 ps
CPU time 45.3 seconds
Started Apr 23 03:23:01 PM PDT 24
Finished Apr 23 03:23:47 PM PDT 24
Peak memory 216824 kb
Host smart-dc4f0f79-9381-4190-b259-ae55ec729b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423342027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.423342027
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.449121650
Short name T510
Test name
Test status
Simulation time 1449082459 ps
CPU time 5.88 seconds
Started Apr 23 03:23:01 PM PDT 24
Finished Apr 23 03:23:08 PM PDT 24
Peak memory 216812 kb
Host smart-16d07a47-6ec8-42db-98a6-052b7ed58940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449121650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.449121650
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.595667334
Short name T58
Test name
Test status
Simulation time 163622682 ps
CPU time 1.22 seconds
Started Apr 23 03:23:00 PM PDT 24
Finished Apr 23 03:23:02 PM PDT 24
Peak memory 216908 kb
Host smart-71e0ac12-738b-433f-9e5d-a29d63949109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595667334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.595667334
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.220202379
Short name T463
Test name
Test status
Simulation time 174261318 ps
CPU time 0.92 seconds
Started Apr 23 03:22:59 PM PDT 24
Finished Apr 23 03:23:01 PM PDT 24
Peak memory 206332 kb
Host smart-961122fd-d038-4f8e-bb55-bf4d290faa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220202379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.220202379
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1756689025
Short name T339
Test name
Test status
Simulation time 19384446761 ps
CPU time 16.21 seconds
Started Apr 23 03:23:08 PM PDT 24
Finished Apr 23 03:23:24 PM PDT 24
Peak memory 216956 kb
Host smart-a3fef7f4-b795-4668-88b7-512dcab240ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756689025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1756689025
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.816702556
Short name T451
Test name
Test status
Simulation time 43536790 ps
CPU time 0.74 seconds
Started Apr 23 03:23:26 PM PDT 24
Finished Apr 23 03:23:27 PM PDT 24
Peak memory 206048 kb
Host smart-1ec0d188-4a28-433a-b045-093b22bd549d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816702556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.816702556
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1587128463
Short name T404
Test name
Test status
Simulation time 78861701 ps
CPU time 0.8 seconds
Started Apr 23 03:23:12 PM PDT 24
Finished Apr 23 03:23:13 PM PDT 24
Peak memory 207204 kb
Host smart-3553aed0-e859-49df-9c54-7a7287877e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587128463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1587128463
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.564749323
Short name T666
Test name
Test status
Simulation time 4396881093 ps
CPU time 29.08 seconds
Started Apr 23 03:23:22 PM PDT 24
Finished Apr 23 03:23:52 PM PDT 24
Peak memory 253992 kb
Host smart-e05c92d6-8327-44d2-b553-569a9fc5f564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564749323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.564749323
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1957228807
Short name T231
Test name
Test status
Simulation time 12386214620 ps
CPU time 10.25 seconds
Started Apr 23 03:23:14 PM PDT 24
Finished Apr 23 03:23:25 PM PDT 24
Peak memory 224128 kb
Host smart-2950aaa8-449a-4c75-9c15-fb8bc67a3012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957228807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1957228807
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.458671915
Short name T224
Test name
Test status
Simulation time 516099745 ps
CPU time 3.91 seconds
Started Apr 23 03:23:15 PM PDT 24
Finished Apr 23 03:23:20 PM PDT 24
Peak memory 219132 kb
Host smart-641f8e59-fca4-423f-821e-1913278c51b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458671915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.458671915
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2436887566
Short name T162
Test name
Test status
Simulation time 171845939 ps
CPU time 4.22 seconds
Started Apr 23 03:23:19 PM PDT 24
Finished Apr 23 03:23:24 PM PDT 24
Peak memory 220884 kb
Host smart-6ecd527a-8dcd-4f19-aefd-03be8049269a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2436887566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2436887566
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.432480526
Short name T638
Test name
Test status
Simulation time 7066943005 ps
CPU time 17.63 seconds
Started Apr 23 03:23:15 PM PDT 24
Finished Apr 23 03:23:33 PM PDT 24
Peak memory 221084 kb
Host smart-a03d9496-c758-4238-a919-d530bdaefbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432480526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.432480526
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.760847846
Short name T101
Test name
Test status
Simulation time 4979770653 ps
CPU time 16.12 seconds
Started Apr 23 03:23:12 PM PDT 24
Finished Apr 23 03:23:29 PM PDT 24
Peak memory 216876 kb
Host smart-7cad8ab5-b8ec-4d07-b8fc-f7d4d0f620e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760847846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.760847846
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1384479999
Short name T502
Test name
Test status
Simulation time 22609886 ps
CPU time 0.94 seconds
Started Apr 23 03:23:16 PM PDT 24
Finished Apr 23 03:23:17 PM PDT 24
Peak memory 207740 kb
Host smart-b5731fcc-5e30-413e-a7e7-6079e50716bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384479999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1384479999
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4074707159
Short name T508
Test name
Test status
Simulation time 242974413 ps
CPU time 1.25 seconds
Started Apr 23 03:23:15 PM PDT 24
Finished Apr 23 03:23:16 PM PDT 24
Peak memory 207380 kb
Host smart-b8266a6d-a78d-4e9c-80bf-ab65e49f6c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074707159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4074707159
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2507082184
Short name T575
Test name
Test status
Simulation time 60489570 ps
CPU time 0.77 seconds
Started Apr 23 03:23:35 PM PDT 24
Finished Apr 23 03:23:36 PM PDT 24
Peak memory 206084 kb
Host smart-bed6cee9-57cc-4f8a-b8dd-bf630c4bfc4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507082184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2507082184
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1579136505
Short name T607
Test name
Test status
Simulation time 1405758158 ps
CPU time 5.46 seconds
Started Apr 23 03:23:34 PM PDT 24
Finished Apr 23 03:23:40 PM PDT 24
Peak memory 223936 kb
Host smart-0d96213b-6f1f-4d57-ac17-83944787321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579136505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1579136505
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2488315878
Short name T414
Test name
Test status
Simulation time 82799003 ps
CPU time 0.74 seconds
Started Apr 23 03:23:26 PM PDT 24
Finished Apr 23 03:23:27 PM PDT 24
Peak memory 206104 kb
Host smart-fff3125f-13fd-4df5-8740-cbb186efb903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488315878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2488315878
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1495492316
Short name T603
Test name
Test status
Simulation time 377935013 ps
CPU time 14.9 seconds
Started Apr 23 03:23:34 PM PDT 24
Finished Apr 23 03:23:49 PM PDT 24
Peak memory 235104 kb
Host smart-e6ef88f4-9d8b-4795-b576-2a7e4b0b0cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495492316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1495492316
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.703087166
Short name T174
Test name
Test status
Simulation time 5352738409 ps
CPU time 7.37 seconds
Started Apr 23 03:23:29 PM PDT 24
Finished Apr 23 03:23:37 PM PDT 24
Peak memory 222880 kb
Host smart-964af666-324b-46f4-a7c3-07a17fd9cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703087166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.703087166
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3470832690
Short name T180
Test name
Test status
Simulation time 79037811 ps
CPU time 3.49 seconds
Started Apr 23 03:23:32 PM PDT 24
Finished Apr 23 03:23:36 PM PDT 24
Peak memory 222996 kb
Host smart-b144d7f7-f314-41df-9093-1fe9da289938
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3470832690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3470832690
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3214855236
Short name T356
Test name
Test status
Simulation time 95516264 ps
CPU time 1.08 seconds
Started Apr 23 03:23:34 PM PDT 24
Finished Apr 23 03:23:36 PM PDT 24
Peak memory 207776 kb
Host smart-ac94ce31-e457-4d23-b26d-58869493d304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214855236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3214855236
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2956920008
Short name T99
Test name
Test status
Simulation time 1131955965 ps
CPU time 11.26 seconds
Started Apr 23 03:23:23 PM PDT 24
Finished Apr 23 03:23:35 PM PDT 24
Peak memory 216808 kb
Host smart-401897c7-14c3-4852-9d75-c9852b0f1b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956920008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2956920008
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1081168709
Short name T587
Test name
Test status
Simulation time 2986172313 ps
CPU time 15.16 seconds
Started Apr 23 03:23:26 PM PDT 24
Finished Apr 23 03:23:41 PM PDT 24
Peak memory 216852 kb
Host smart-46e757d8-13f8-4632-bf3e-20acba77b46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081168709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1081168709
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.994752527
Short name T541
Test name
Test status
Simulation time 24388650 ps
CPU time 0.88 seconds
Started Apr 23 03:23:27 PM PDT 24
Finished Apr 23 03:23:28 PM PDT 24
Peak memory 206864 kb
Host smart-d666b671-c5e2-4f11-a2fe-5f921993c61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994752527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.994752527
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2026130890
Short name T489
Test name
Test status
Simulation time 24485370 ps
CPU time 0.8 seconds
Started Apr 23 03:23:30 PM PDT 24
Finished Apr 23 03:23:31 PM PDT 24
Peak memory 206348 kb
Host smart-0a61a467-40bc-4a9d-8c1a-637dc26a2332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026130890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2026130890
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3179033686
Short name T644
Test name
Test status
Simulation time 13051844 ps
CPU time 0.68 seconds
Started Apr 23 03:23:48 PM PDT 24
Finished Apr 23 03:23:49 PM PDT 24
Peak memory 206020 kb
Host smart-cd7302be-1f4d-4506-b02a-c8be1b6a0c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179033686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3179033686
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3485173203
Short name T25
Test name
Test status
Simulation time 814775446 ps
CPU time 7.57 seconds
Started Apr 23 03:23:46 PM PDT 24
Finished Apr 23 03:23:54 PM PDT 24
Peak memory 225052 kb
Host smart-2a0ba01a-3de5-441e-8633-d87c1899afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485173203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3485173203
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1009774864
Short name T434
Test name
Test status
Simulation time 38956902 ps
CPU time 0.71 seconds
Started Apr 23 03:23:35 PM PDT 24
Finished Apr 23 03:23:36 PM PDT 24
Peak memory 206152 kb
Host smart-c75ed40d-68d8-49a0-ba01-4a30b2892b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009774864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1009774864
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1498227777
Short name T609
Test name
Test status
Simulation time 3633427511 ps
CPU time 55.22 seconds
Started Apr 23 03:23:45 PM PDT 24
Finished Apr 23 03:24:41 PM PDT 24
Peak memory 241408 kb
Host smart-e9bea86f-7e3f-436a-b52c-5e362a6231ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498227777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1498227777
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3932652901
Short name T334
Test name
Test status
Simulation time 22336415774 ps
CPU time 83.43 seconds
Started Apr 23 03:23:46 PM PDT 24
Finished Apr 23 03:25:10 PM PDT 24
Peak memory 224892 kb
Host smart-65051f67-be8b-4032-ba27-99035241c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932652901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3932652901
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3444990872
Short name T262
Test name
Test status
Simulation time 530125218 ps
CPU time 3.24 seconds
Started Apr 23 03:23:46 PM PDT 24
Finished Apr 23 03:23:49 PM PDT 24
Peak memory 222584 kb
Host smart-3648f1f7-bf1d-4b07-ab5b-1f421836bc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444990872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3444990872
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1233703896
Short name T241
Test name
Test status
Simulation time 798181296 ps
CPU time 5.52 seconds
Started Apr 23 03:23:42 PM PDT 24
Finished Apr 23 03:23:48 PM PDT 24
Peak memory 224216 kb
Host smart-a8482809-9ca2-4f02-8ef7-46a64fc43641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233703896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1233703896
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.803820962
Short name T543
Test name
Test status
Simulation time 4272826430 ps
CPU time 14.09 seconds
Started Apr 23 03:23:46 PM PDT 24
Finished Apr 23 03:24:01 PM PDT 24
Peak memory 223544 kb
Host smart-c3d0140b-c879-46a2-8f97-b299232d1db4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=803820962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.803820962
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2364028981
Short name T475
Test name
Test status
Simulation time 1349254913 ps
CPU time 4.86 seconds
Started Apr 23 03:23:37 PM PDT 24
Finished Apr 23 03:23:43 PM PDT 24
Peak memory 216908 kb
Host smart-f4842801-1bb9-479c-9d6b-35aebfbcbb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364028981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2364028981
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2364559204
Short name T432
Test name
Test status
Simulation time 394072363 ps
CPU time 1.55 seconds
Started Apr 23 03:23:39 PM PDT 24
Finished Apr 23 03:23:41 PM PDT 24
Peak memory 208448 kb
Host smart-2f9ffe57-b3f2-484b-8d3f-15b406d4df69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364559204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2364559204
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3664581482
Short name T425
Test name
Test status
Simulation time 319092874 ps
CPU time 2.15 seconds
Started Apr 23 03:23:41 PM PDT 24
Finished Apr 23 03:23:44 PM PDT 24
Peak memory 216832 kb
Host smart-c40728ff-b951-4162-ace9-1e1cf2547b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664581482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3664581482
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3904390177
Short name T610
Test name
Test status
Simulation time 393712881 ps
CPU time 1.04 seconds
Started Apr 23 03:23:39 PM PDT 24
Finished Apr 23 03:23:41 PM PDT 24
Peak memory 207388 kb
Host smart-f9eaee05-3f54-40af-a295-fd5c006037dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904390177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3904390177
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2190166332
Short name T375
Test name
Test status
Simulation time 921383781 ps
CPU time 6.42 seconds
Started Apr 23 03:23:45 PM PDT 24
Finished Apr 23 03:23:51 PM PDT 24
Peak memory 225016 kb
Host smart-f13c77e4-45bc-443a-8a7d-a07d07a80744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190166332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2190166332
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1158755619
Short name T413
Test name
Test status
Simulation time 185687657 ps
CPU time 0.74 seconds
Started Apr 23 03:24:03 PM PDT 24
Finished Apr 23 03:24:04 PM PDT 24
Peak memory 205440 kb
Host smart-eaf0a802-708d-462b-a2d3-452c1ad9231d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158755619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1158755619
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.872248267
Short name T500
Test name
Test status
Simulation time 15792333 ps
CPU time 0.77 seconds
Started Apr 23 03:23:52 PM PDT 24
Finished Apr 23 03:23:53 PM PDT 24
Peak memory 207188 kb
Host smart-1a9bc886-5d2f-456b-bbc0-52fea742d51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872248267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.872248267
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3144726430
Short name T298
Test name
Test status
Simulation time 21469732333 ps
CPU time 85.31 seconds
Started Apr 23 03:23:56 PM PDT 24
Finished Apr 23 03:25:22 PM PDT 24
Peak memory 250096 kb
Host smart-2858ff85-94fd-4d6f-b089-d17755537695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144726430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3144726430
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3935427711
Short name T8
Test name
Test status
Simulation time 46320744827 ps
CPU time 19.15 seconds
Started Apr 23 03:23:55 PM PDT 24
Finished Apr 23 03:24:14 PM PDT 24
Peak memory 224948 kb
Host smart-a3ac5c24-5c6b-4d2e-808d-4207fb5d617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935427711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3935427711
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.46828072
Short name T497
Test name
Test status
Simulation time 1807340791 ps
CPU time 12.71 seconds
Started Apr 23 03:24:01 PM PDT 24
Finished Apr 23 03:24:14 PM PDT 24
Peak memory 220304 kb
Host smart-b4a44b91-3460-4819-a6a6-04a033ad0732
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=46828072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direc
t.46828072
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4116006513
Short name T490
Test name
Test status
Simulation time 3563868985 ps
CPU time 12.07 seconds
Started Apr 23 03:23:51 PM PDT 24
Finished Apr 23 03:24:04 PM PDT 24
Peak memory 216852 kb
Host smart-9aa62c24-4f16-45f8-965b-846ab1ff7ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116006513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4116006513
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2760634083
Short name T582
Test name
Test status
Simulation time 71442818 ps
CPU time 1.23 seconds
Started Apr 23 03:23:56 PM PDT 24
Finished Apr 23 03:23:57 PM PDT 24
Peak memory 208448 kb
Host smart-71c565a9-0bad-433b-813e-59031353318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760634083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2760634083
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1255692933
Short name T584
Test name
Test status
Simulation time 118405897 ps
CPU time 0.84 seconds
Started Apr 23 03:23:55 PM PDT 24
Finished Apr 23 03:23:56 PM PDT 24
Peak memory 206352 kb
Host smart-2120bd4f-3f2e-450e-8b2a-e5d6d6d85de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255692933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1255692933
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.195910137
Short name T27
Test name
Test status
Simulation time 3621460787 ps
CPU time 7.97 seconds
Started Apr 23 03:24:01 PM PDT 24
Finished Apr 23 03:24:10 PM PDT 24
Peak memory 237416 kb
Host smart-60e27ced-0118-4ddc-a450-6a030078f971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195910137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.195910137
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.978164437
Short name T689
Test name
Test status
Simulation time 12672979 ps
CPU time 0.74 seconds
Started Apr 23 03:24:12 PM PDT 24
Finished Apr 23 03:24:13 PM PDT 24
Peak memory 206076 kb
Host smart-27b83076-38eb-47fe-acd1-076d52c806a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978164437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.978164437
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2766235171
Short name T84
Test name
Test status
Simulation time 511039523 ps
CPU time 3.15 seconds
Started Apr 23 03:24:09 PM PDT 24
Finished Apr 23 03:24:13 PM PDT 24
Peak memory 217916 kb
Host smart-f3414f9b-2722-4789-87c2-db8550e9f58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766235171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2766235171
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.471161876
Short name T592
Test name
Test status
Simulation time 50553165 ps
CPU time 0.8 seconds
Started Apr 23 03:24:02 PM PDT 24
Finished Apr 23 03:24:04 PM PDT 24
Peak memory 207440 kb
Host smart-63135d12-f5c7-477e-996b-4b45f657b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471161876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.471161876
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1617185495
Short name T366
Test name
Test status
Simulation time 5624372358 ps
CPU time 73.77 seconds
Started Apr 23 03:24:10 PM PDT 24
Finished Apr 23 03:25:24 PM PDT 24
Peak memory 225124 kb
Host smart-85bc0455-5734-49bf-8afc-0e9414dccd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617185495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1617185495
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2976617545
Short name T79
Test name
Test status
Simulation time 20633726584 ps
CPU time 15.09 seconds
Started Apr 23 03:24:06 PM PDT 24
Finished Apr 23 03:24:21 PM PDT 24
Peak memory 227652 kb
Host smart-add88541-d990-4ccb-a6f4-9e354b0a643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976617545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2976617545
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3303583451
Short name T667
Test name
Test status
Simulation time 5601688172 ps
CPU time 15.05 seconds
Started Apr 23 03:24:07 PM PDT 24
Finished Apr 23 03:24:23 PM PDT 24
Peak memory 219588 kb
Host smart-2e3188ae-254e-4f34-b750-85a68092af93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3303583451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3303583451
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3097648345
Short name T40
Test name
Test status
Simulation time 41323288 ps
CPU time 0.88 seconds
Started Apr 23 03:24:11 PM PDT 24
Finished Apr 23 03:24:12 PM PDT 24
Peak memory 207444 kb
Host smart-3805ae9c-16a6-4d55-9b48-f2218c2ac960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097648345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3097648345
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1385162388
Short name T578
Test name
Test status
Simulation time 1838187553 ps
CPU time 24.72 seconds
Started Apr 23 03:24:03 PM PDT 24
Finished Apr 23 03:24:28 PM PDT 24
Peak memory 216844 kb
Host smart-94c33804-71a5-4d9c-970b-6a5779600933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385162388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1385162388
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3809948449
Short name T407
Test name
Test status
Simulation time 1509023212 ps
CPU time 4.24 seconds
Started Apr 23 03:24:02 PM PDT 24
Finished Apr 23 03:24:06 PM PDT 24
Peak memory 216780 kb
Host smart-c8df2b63-a760-4fdb-8652-08533926eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809948449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3809948449
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3026210260
Short name T514
Test name
Test status
Simulation time 144865218 ps
CPU time 4.76 seconds
Started Apr 23 03:24:05 PM PDT 24
Finished Apr 23 03:24:10 PM PDT 24
Peak memory 216816 kb
Host smart-9cf21559-223c-4aa4-9f7d-30bc8017a3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026210260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3026210260
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.714738718
Short name T104
Test name
Test status
Simulation time 120450849 ps
CPU time 0.78 seconds
Started Apr 23 03:24:02 PM PDT 24
Finished Apr 23 03:24:04 PM PDT 24
Peak memory 206340 kb
Host smart-b0287786-f596-4a24-a7af-d6b3426bf522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714738718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.714738718
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.666091199
Short name T376
Test name
Test status
Simulation time 57684402239 ps
CPU time 14.55 seconds
Started Apr 23 03:24:08 PM PDT 24
Finished Apr 23 03:24:23 PM PDT 24
Peak memory 233336 kb
Host smart-1c2882b1-add9-4c76-80bb-dcfc9470dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666091199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.666091199
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.231051437
Short name T622
Test name
Test status
Simulation time 12894354 ps
CPU time 0.73 seconds
Started Apr 23 03:24:22 PM PDT 24
Finished Apr 23 03:24:24 PM PDT 24
Peak memory 206032 kb
Host smart-e5199365-635a-41f2-befe-6ae15f52a2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231051437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.231051437
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.580310814
Short name T707
Test name
Test status
Simulation time 22318646 ps
CPU time 0.8 seconds
Started Apr 23 03:24:10 PM PDT 24
Finished Apr 23 03:24:11 PM PDT 24
Peak memory 207132 kb
Host smart-86d20fe6-13c5-4d71-ad2a-9f0d7c3898eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580310814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.580310814
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4196508038
Short name T119
Test name
Test status
Simulation time 5427118379 ps
CPU time 21.77 seconds
Started Apr 23 03:24:18 PM PDT 24
Finished Apr 23 03:24:40 PM PDT 24
Peak memory 241364 kb
Host smart-c23775a6-b444-4e07-8549-285372aa264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196508038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4196508038
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2894401113
Short name T324
Test name
Test status
Simulation time 3770938376 ps
CPU time 13.86 seconds
Started Apr 23 03:24:14 PM PDT 24
Finished Apr 23 03:24:28 PM PDT 24
Peak memory 233148 kb
Host smart-20d79fc5-8cb1-4fc2-a381-f5dc307f7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894401113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2894401113
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.885147497
Short name T423
Test name
Test status
Simulation time 3345381415 ps
CPU time 9.35 seconds
Started Apr 23 03:24:18 PM PDT 24
Finished Apr 23 03:24:27 PM PDT 24
Peak memory 219300 kb
Host smart-e1b42f4b-90ff-4341-8fef-a82befe72a24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=885147497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.885147497
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1453592677
Short name T382
Test name
Test status
Simulation time 6229379445 ps
CPU time 44.42 seconds
Started Apr 23 03:24:15 PM PDT 24
Finished Apr 23 03:25:00 PM PDT 24
Peak memory 217176 kb
Host smart-3a7a50e0-fc2e-4c96-86f4-88ce304bd1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453592677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1453592677
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3889846556
Short name T411
Test name
Test status
Simulation time 21558294317 ps
CPU time 10.59 seconds
Started Apr 23 03:24:10 PM PDT 24
Finished Apr 23 03:24:21 PM PDT 24
Peak memory 216864 kb
Host smart-e06eb91a-9937-4a1a-b7a1-349d19b2acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889846556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3889846556
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.470730359
Short name T663
Test name
Test status
Simulation time 106868194 ps
CPU time 1.39 seconds
Started Apr 23 03:24:14 PM PDT 24
Finished Apr 23 03:24:16 PM PDT 24
Peak memory 216680 kb
Host smart-f996a0b8-bf3b-4cee-8336-0bcd116fc5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470730359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.470730359
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3573180064
Short name T513
Test name
Test status
Simulation time 67513421 ps
CPU time 0.89 seconds
Started Apr 23 03:24:14 PM PDT 24
Finished Apr 23 03:24:15 PM PDT 24
Peak memory 207384 kb
Host smart-8e953d76-ce82-45a6-b1f7-9a1b6752fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573180064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3573180064
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1223569054
Short name T12
Test name
Test status
Simulation time 57040767 ps
CPU time 2.44 seconds
Started Apr 23 03:24:14 PM PDT 24
Finished Apr 23 03:24:17 PM PDT 24
Peak memory 222208 kb
Host smart-cb04d27c-49d1-4225-a47f-8a461fd7e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223569054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1223569054
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2722610168
Short name T620
Test name
Test status
Simulation time 21799796 ps
CPU time 0.71 seconds
Started Apr 23 03:24:36 PM PDT 24
Finished Apr 23 03:24:37 PM PDT 24
Peak memory 206044 kb
Host smart-1d16ef1d-7bed-429a-ba1c-ebb5249721f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722610168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2722610168
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3379967742
Short name T665
Test name
Test status
Simulation time 16047364 ps
CPU time 0.73 seconds
Started Apr 23 03:24:22 PM PDT 24
Finished Apr 23 03:24:23 PM PDT 24
Peak memory 206084 kb
Host smart-bf0d2a6b-8234-40d6-b8be-a68f9557af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379967742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3379967742
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3921957684
Short name T80
Test name
Test status
Simulation time 1973958287 ps
CPU time 19.26 seconds
Started Apr 23 03:24:32 PM PDT 24
Finished Apr 23 03:24:52 PM PDT 24
Peak memory 249612 kb
Host smart-86c9c9bc-b643-41c0-af7e-7b204391eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921957684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3921957684
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3342078043
Short name T212
Test name
Test status
Simulation time 2998629015 ps
CPU time 32.89 seconds
Started Apr 23 03:24:28 PM PDT 24
Finished Apr 23 03:25:01 PM PDT 24
Peak memory 224296 kb
Host smart-bc1b7fe2-77b9-4672-bc55-474e07eac256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342078043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3342078043
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.793500363
Short name T274
Test name
Test status
Simulation time 680921019 ps
CPU time 8.67 seconds
Started Apr 23 03:24:23 PM PDT 24
Finished Apr 23 03:24:32 PM PDT 24
Peak memory 237908 kb
Host smart-c914439b-39f0-44fe-9619-ea477eb1bf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793500363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.793500363
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3955485235
Short name T534
Test name
Test status
Simulation time 611726868 ps
CPU time 7.74 seconds
Started Apr 23 03:24:32 PM PDT 24
Finished Apr 23 03:24:40 PM PDT 24
Peak memory 220932 kb
Host smart-2a92ce80-f79b-4c48-ae63-35b8b3158b6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3955485235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3955485235
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3173851300
Short name T38
Test name
Test status
Simulation time 268604263 ps
CPU time 0.89 seconds
Started Apr 23 03:24:36 PM PDT 24
Finished Apr 23 03:24:37 PM PDT 24
Peak memory 207152 kb
Host smart-a48d54fc-4467-4cf7-add2-1bd7838caf02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173851300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3173851300
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1558218598
Short name T692
Test name
Test status
Simulation time 7551368662 ps
CPU time 19.23 seconds
Started Apr 23 03:24:20 PM PDT 24
Finished Apr 23 03:24:40 PM PDT 24
Peak memory 216884 kb
Host smart-9fef117b-30ea-4209-b7df-b0937f8df047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558218598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1558218598
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.824181623
Short name T398
Test name
Test status
Simulation time 19802840 ps
CPU time 0.83 seconds
Started Apr 23 03:24:24 PM PDT 24
Finished Apr 23 03:24:26 PM PDT 24
Peak memory 206992 kb
Host smart-83603c89-7d4d-4522-b101-11ccd2e199da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824181623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.824181623
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.856259062
Short name T676
Test name
Test status
Simulation time 129564388 ps
CPU time 0.78 seconds
Started Apr 23 03:24:22 PM PDT 24
Finished Apr 23 03:24:24 PM PDT 24
Peak memory 206240 kb
Host smart-602b0a0e-7b12-4913-84ce-5940181f5a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856259062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.856259062
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3304549756
Short name T179
Test name
Test status
Simulation time 29617997 ps
CPU time 0.68 seconds
Started Apr 23 03:24:50 PM PDT 24
Finished Apr 23 03:24:51 PM PDT 24
Peak memory 206048 kb
Host smart-4de1a752-adf6-4164-9617-3b55b4ea4146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304549756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3304549756
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1288878505
Short name T579
Test name
Test status
Simulation time 16285136 ps
CPU time 0.82 seconds
Started Apr 23 03:24:35 PM PDT 24
Finished Apr 23 03:24:37 PM PDT 24
Peak memory 207492 kb
Host smart-8d97bb51-444c-49eb-9d45-5efef8ee608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288878505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1288878505
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.998270498
Short name T307
Test name
Test status
Simulation time 583356427 ps
CPU time 11.06 seconds
Started Apr 23 03:24:45 PM PDT 24
Finished Apr 23 03:24:57 PM PDT 24
Peak memory 236076 kb
Host smart-a28d2883-ea85-4a04-8fe9-8afe04d956c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998270498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.998270498
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2424243301
Short name T357
Test name
Test status
Simulation time 3029159079 ps
CPU time 15.11 seconds
Started Apr 23 03:24:43 PM PDT 24
Finished Apr 23 03:24:58 PM PDT 24
Peak memory 224876 kb
Host smart-281ca419-aca2-4ced-9633-9967eda55f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424243301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2424243301
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2488072377
Short name T88
Test name
Test status
Simulation time 6182053677 ps
CPU time 12.54 seconds
Started Apr 23 03:24:43 PM PDT 24
Finished Apr 23 03:24:56 PM PDT 24
Peak memory 217460 kb
Host smart-5be53b9c-1eed-460a-868b-fdb8f4fd2a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488072377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2488072377
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3022619483
Short name T522
Test name
Test status
Simulation time 3301657673 ps
CPU time 10.17 seconds
Started Apr 23 03:24:45 PM PDT 24
Finished Apr 23 03:24:56 PM PDT 24
Peak memory 222648 kb
Host smart-d3d1f857-ac72-4868-9d66-0eb34d19628e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3022619483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3022619483
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2354479923
Short name T695
Test name
Test status
Simulation time 241744483 ps
CPU time 1.96 seconds
Started Apr 23 03:24:35 PM PDT 24
Finished Apr 23 03:24:38 PM PDT 24
Peak memory 216632 kb
Host smart-3317105b-3b99-40f7-ae4e-da2ed0f14077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354479923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2354479923
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2391594836
Short name T639
Test name
Test status
Simulation time 109984150 ps
CPU time 1.17 seconds
Started Apr 23 03:24:41 PM PDT 24
Finished Apr 23 03:24:43 PM PDT 24
Peak memory 216856 kb
Host smart-38bf4f39-dcdf-4a5f-8881-4cf03009ff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391594836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2391594836
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4278139821
Short name T467
Test name
Test status
Simulation time 95249672 ps
CPU time 0.85 seconds
Started Apr 23 03:24:39 PM PDT 24
Finished Apr 23 03:24:41 PM PDT 24
Peak memory 206352 kb
Host smart-8a4952a6-d505-4a73-9bf8-8b068386025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278139821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4278139821
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1653037234
Short name T512
Test name
Test status
Simulation time 15527783 ps
CPU time 0.7 seconds
Started Apr 23 03:24:58 PM PDT 24
Finished Apr 23 03:24:59 PM PDT 24
Peak memory 206396 kb
Host smart-bbcf90d2-9fd3-4f39-9d52-fbadc1c60f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653037234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1653037234
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2584153633
Short name T439
Test name
Test status
Simulation time 17923807 ps
CPU time 0.78 seconds
Started Apr 23 03:24:47 PM PDT 24
Finished Apr 23 03:24:48 PM PDT 24
Peak memory 207452 kb
Host smart-7924490a-d104-4920-97ea-426f0fc54468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584153633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2584153633
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1788635988
Short name T291
Test name
Test status
Simulation time 3369445105 ps
CPU time 38.53 seconds
Started Apr 23 03:24:57 PM PDT 24
Finished Apr 23 03:25:36 PM PDT 24
Peak memory 249648 kb
Host smart-cf8b81f7-91e4-414a-855f-720d8540ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788635988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1788635988
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3527233537
Short name T647
Test name
Test status
Simulation time 1167084270 ps
CPU time 14.77 seconds
Started Apr 23 03:24:55 PM PDT 24
Finished Apr 23 03:25:10 PM PDT 24
Peak memory 223592 kb
Host smart-db10080e-1654-4a25-87b3-0a100d62c4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527233537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3527233537
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1625472820
Short name T288
Test name
Test status
Simulation time 1643813681 ps
CPU time 3.71 seconds
Started Apr 23 03:24:53 PM PDT 24
Finished Apr 23 03:24:57 PM PDT 24
Peak memory 218956 kb
Host smart-78e25417-4291-4c7a-b33c-69151b4f2298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625472820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1625472820
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.314854903
Short name T219
Test name
Test status
Simulation time 149748525 ps
CPU time 2.67 seconds
Started Apr 23 03:24:53 PM PDT 24
Finished Apr 23 03:24:56 PM PDT 24
Peak memory 219200 kb
Host smart-bf2b2b32-940c-483b-b650-7ce79efe29a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314854903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.314854903
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1631815951
Short name T540
Test name
Test status
Simulation time 393344978 ps
CPU time 3.89 seconds
Started Apr 23 03:24:57 PM PDT 24
Finished Apr 23 03:25:01 PM PDT 24
Peak memory 223396 kb
Host smart-4fef4035-e273-4e45-92ea-8dbf12199ce2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1631815951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1631815951
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3607031710
Short name T175
Test name
Test status
Simulation time 3875660412 ps
CPU time 34.82 seconds
Started Apr 23 03:24:51 PM PDT 24
Finished Apr 23 03:25:27 PM PDT 24
Peak memory 216904 kb
Host smart-e98562a3-c664-4037-9f6f-a619beace18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607031710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3607031710
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2189454248
Short name T417
Test name
Test status
Simulation time 5787150904 ps
CPU time 7.15 seconds
Started Apr 23 03:24:50 PM PDT 24
Finished Apr 23 03:24:57 PM PDT 24
Peak memory 216876 kb
Host smart-a42b8fe9-9202-48ef-96ca-68ef95002cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189454248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2189454248
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1395720891
Short name T22
Test name
Test status
Simulation time 145295468 ps
CPU time 4.31 seconds
Started Apr 23 03:24:51 PM PDT 24
Finished Apr 23 03:24:55 PM PDT 24
Peak memory 216868 kb
Host smart-147fb490-91cf-4382-a7f3-7e96512dba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395720891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1395720891
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1877674082
Short name T14
Test name
Test status
Simulation time 58661605 ps
CPU time 0.97 seconds
Started Apr 23 03:24:52 PM PDT 24
Finished Apr 23 03:24:53 PM PDT 24
Peak memory 207360 kb
Host smart-3089112b-6e50-491c-8289-9da2a139831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877674082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1877674082
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2521523480
Short name T264
Test name
Test status
Simulation time 836226995 ps
CPU time 2.83 seconds
Started Apr 23 03:24:55 PM PDT 24
Finished Apr 23 03:24:59 PM PDT 24
Peak memory 216776 kb
Host smart-460b0884-d4fe-43cf-b98e-6d9ed2407ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521523480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2521523480
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1562017246
Short name T505
Test name
Test status
Simulation time 11270453 ps
CPU time 0.73 seconds
Started Apr 23 03:15:48 PM PDT 24
Finished Apr 23 03:15:49 PM PDT 24
Peak memory 205412 kb
Host smart-5385d690-005f-49b5-a82b-af53cf0a4cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562017246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
562017246
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3168769067
Short name T422
Test name
Test status
Simulation time 31426665 ps
CPU time 0.78 seconds
Started Apr 23 03:15:32 PM PDT 24
Finished Apr 23 03:15:34 PM PDT 24
Peak memory 207180 kb
Host smart-eb61c421-926d-46f0-bb9e-bb1b438094f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168769067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3168769067
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3141354370
Short name T108
Test name
Test status
Simulation time 2689089326 ps
CPU time 56.24 seconds
Started Apr 23 03:15:42 PM PDT 24
Finished Apr 23 03:16:39 PM PDT 24
Peak memory 236852 kb
Host smart-e4f9c709-ebc2-43f3-8761-3d13be50615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141354370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3141354370
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.538988191
Short name T87
Test name
Test status
Simulation time 442570810 ps
CPU time 7.83 seconds
Started Apr 23 03:15:33 PM PDT 24
Finished Apr 23 03:15:41 PM PDT 24
Peak memory 223596 kb
Host smart-8eff21ca-2fb9-40b4-9735-8c0b756c0519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538988191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.538988191
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.423272245
Short name T268
Test name
Test status
Simulation time 665560674 ps
CPU time 4.09 seconds
Started Apr 23 03:15:35 PM PDT 24
Finished Apr 23 03:15:39 PM PDT 24
Peak memory 217292 kb
Host smart-dfb9c352-2c8f-4b50-a019-16e425ee731a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423272245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.423272245
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2293447588
Short name T159
Test name
Test status
Simulation time 444472787 ps
CPU time 4.04 seconds
Started Apr 23 03:15:43 PM PDT 24
Finished Apr 23 03:15:47 PM PDT 24
Peak memory 222976 kb
Host smart-90a324f4-9b80-43cf-9526-ce4e79a9dc48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2293447588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2293447588
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1020789978
Short name T387
Test name
Test status
Simulation time 644617323 ps
CPU time 4.04 seconds
Started Apr 23 03:15:32 PM PDT 24
Finished Apr 23 03:15:38 PM PDT 24
Peak memory 218720 kb
Host smart-f351bc32-321e-4401-a517-911121858cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020789978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1020789978
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1335748698
Short name T178
Test name
Test status
Simulation time 4750308151 ps
CPU time 8.84 seconds
Started Apr 23 03:15:31 PM PDT 24
Finished Apr 23 03:15:42 PM PDT 24
Peak memory 216868 kb
Host smart-01d13c14-bd85-449c-9a06-97d94db6c214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335748698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1335748698
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.799547330
Short name T506
Test name
Test status
Simulation time 324612101 ps
CPU time 7.02 seconds
Started Apr 23 03:15:35 PM PDT 24
Finished Apr 23 03:15:42 PM PDT 24
Peak memory 216760 kb
Host smart-3938768a-15a5-4726-a7ae-e3b56ec0ca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799547330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.799547330
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2784179556
Short name T452
Test name
Test status
Simulation time 106646384 ps
CPU time 0.92 seconds
Started Apr 23 03:15:34 PM PDT 24
Finished Apr 23 03:15:36 PM PDT 24
Peak memory 207388 kb
Host smart-8fb1c96a-6eca-4e68-a065-217a3c2dae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784179556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2784179556
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1448285659
Short name T438
Test name
Test status
Simulation time 13107191 ps
CPU time 0.74 seconds
Started Apr 23 03:15:59 PM PDT 24
Finished Apr 23 03:16:00 PM PDT 24
Peak memory 206000 kb
Host smart-dcc68346-06ad-47c0-8581-169775eb7a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448285659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
448285659
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.419132610
Short name T431
Test name
Test status
Simulation time 68420386 ps
CPU time 0.76 seconds
Started Apr 23 03:15:50 PM PDT 24
Finished Apr 23 03:15:52 PM PDT 24
Peak memory 207192 kb
Host smart-9faba6f9-c950-4c69-81d8-4c70aac5b240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419132610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.419132610
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.748871232
Short name T296
Test name
Test status
Simulation time 24351756836 ps
CPU time 94.75 seconds
Started Apr 23 03:15:51 PM PDT 24
Finished Apr 23 03:17:26 PM PDT 24
Peak memory 250720 kb
Host smart-01864145-504b-4df9-a162-a6847251db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748871232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.748871232
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3929801229
Short name T204
Test name
Test status
Simulation time 425507323 ps
CPU time 2.65 seconds
Started Apr 23 03:15:52 PM PDT 24
Finished Apr 23 03:15:55 PM PDT 24
Peak memory 217164 kb
Host smart-2a5d3809-a0f2-43ad-97b8-2b62860ce3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929801229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3929801229
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2280855370
Short name T183
Test name
Test status
Simulation time 1791613557 ps
CPU time 10.32 seconds
Started Apr 23 03:15:51 PM PDT 24
Finished Apr 23 03:16:02 PM PDT 24
Peak memory 222984 kb
Host smart-71b8d930-5738-4fa7-856a-dfc41fcad1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280855370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2280855370
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2726171483
Short name T160
Test name
Test status
Simulation time 158776366 ps
CPU time 4.36 seconds
Started Apr 23 03:15:55 PM PDT 24
Finished Apr 23 03:16:00 PM PDT 24
Peak memory 220608 kb
Host smart-e0ec2230-8c9b-4a90-9eef-0fc3e363e70d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2726171483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2726171483
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.344966605
Short name T560
Test name
Test status
Simulation time 1416172495 ps
CPU time 7.58 seconds
Started Apr 23 03:15:48 PM PDT 24
Finished Apr 23 03:15:56 PM PDT 24
Peak memory 216796 kb
Host smart-151fc439-002e-4c01-9869-8ec460787dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344966605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.344966605
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4275688637
Short name T443
Test name
Test status
Simulation time 14809497480 ps
CPU time 9.28 seconds
Started Apr 23 03:15:49 PM PDT 24
Finished Apr 23 03:15:59 PM PDT 24
Peak memory 216912 kb
Host smart-9fcde15c-f791-4d41-b576-f9a069c456c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275688637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4275688637
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1909700790
Short name T718
Test name
Test status
Simulation time 22949638 ps
CPU time 0.94 seconds
Started Apr 23 03:15:49 PM PDT 24
Finished Apr 23 03:15:50 PM PDT 24
Peak memory 207432 kb
Host smart-df71b8c0-fdc9-4e68-aa12-b2651fd58659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909700790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1909700790
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.381197246
Short name T410
Test name
Test status
Simulation time 123069832 ps
CPU time 1.04 seconds
Started Apr 23 03:15:48 PM PDT 24
Finished Apr 23 03:15:50 PM PDT 24
Peak memory 206804 kb
Host smart-d0d69c10-215c-4965-803e-3f8e6424e66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381197246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.381197246
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.509475433
Short name T177
Test name
Test status
Simulation time 2503310457 ps
CPU time 7.32 seconds
Started Apr 23 03:15:50 PM PDT 24
Finished Apr 23 03:15:58 PM PDT 24
Peak memory 224236 kb
Host smart-ac72654e-8be1-477d-8f0f-4c9310535b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509475433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.509475433
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3895793150
Short name T614
Test name
Test status
Simulation time 20108497 ps
CPU time 0.7 seconds
Started Apr 23 03:16:09 PM PDT 24
Finished Apr 23 03:16:10 PM PDT 24
Peak memory 206060 kb
Host smart-ab4d0e53-b268-45a5-b903-63ae29b0520f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895793150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
895793150
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3058182024
Short name T189
Test name
Test status
Simulation time 3885367146 ps
CPU time 15.29 seconds
Started Apr 23 03:16:08 PM PDT 24
Finished Apr 23 03:16:24 PM PDT 24
Peak memory 233268 kb
Host smart-4a2aead0-5e5d-41f4-bf7b-372bdeb7fc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058182024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3058182024
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3327997126
Short name T568
Test name
Test status
Simulation time 17557961 ps
CPU time 0.77 seconds
Started Apr 23 03:16:00 PM PDT 24
Finished Apr 23 03:16:01 PM PDT 24
Peak memory 206060 kb
Host smart-ca567bbf-36f3-4681-b078-911febab284e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327997126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3327997126
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4245922298
Short name T700
Test name
Test status
Simulation time 3377117234 ps
CPU time 33.01 seconds
Started Apr 23 03:16:07 PM PDT 24
Finished Apr 23 03:16:41 PM PDT 24
Peak memory 233264 kb
Host smart-e6d7daf1-f452-4c9e-b362-c5e835460620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245922298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4245922298
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3218725005
Short name T310
Test name
Test status
Simulation time 382154415 ps
CPU time 5.34 seconds
Started Apr 23 03:16:08 PM PDT 24
Finished Apr 23 03:16:15 PM PDT 24
Peak memory 217292 kb
Host smart-cbd09fa9-d3b7-4f93-94c9-f54c3678c082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218725005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3218725005
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.124974189
Short name T367
Test name
Test status
Simulation time 44219714 ps
CPU time 2.79 seconds
Started Apr 23 03:16:05 PM PDT 24
Finished Apr 23 03:16:09 PM PDT 24
Peak memory 223048 kb
Host smart-a86830c6-2025-4a9a-a03b-867dae3bca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124974189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.124974189
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1108695959
Short name T713
Test name
Test status
Simulation time 948809665 ps
CPU time 3.92 seconds
Started Apr 23 03:16:07 PM PDT 24
Finished Apr 23 03:16:11 PM PDT 24
Peak memory 220520 kb
Host smart-781b038d-ab71-425e-814b-2b1ba8eec928
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1108695959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1108695959
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.985569496
Short name T616
Test name
Test status
Simulation time 991044529 ps
CPU time 13.12 seconds
Started Apr 23 03:16:02 PM PDT 24
Finished Apr 23 03:16:16 PM PDT 24
Peak memory 216804 kb
Host smart-9d1d29bc-0d5d-48bf-932e-c440cd34ec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985569496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.985569496
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1964729650
Short name T653
Test name
Test status
Simulation time 4854822478 ps
CPU time 7.72 seconds
Started Apr 23 03:16:02 PM PDT 24
Finished Apr 23 03:16:11 PM PDT 24
Peak memory 216892 kb
Host smart-c8badd57-b31a-4632-bbc2-5acb962e10f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964729650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1964729650
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.484570454
Short name T538
Test name
Test status
Simulation time 20782955 ps
CPU time 0.74 seconds
Started Apr 23 03:16:09 PM PDT 24
Finished Apr 23 03:16:10 PM PDT 24
Peak memory 206316 kb
Host smart-fa13798d-e8ba-4b1e-bd40-cc5eeaa708ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484570454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.484570454
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1719154861
Short name T405
Test name
Test status
Simulation time 76711833 ps
CPU time 0.96 seconds
Started Apr 23 03:16:06 PM PDT 24
Finished Apr 23 03:16:07 PM PDT 24
Peak memory 206348 kb
Host smart-3c35eea7-9b92-4ca1-8cd0-adfab39d1507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719154861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1719154861
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3143724730
Short name T257
Test name
Test status
Simulation time 178510224799 ps
CPU time 47.62 seconds
Started Apr 23 03:16:10 PM PDT 24
Finished Apr 23 03:16:58 PM PDT 24
Peak memory 232488 kb
Host smart-eaf14ed2-0cc0-4158-a882-06f69549de25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143724730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3143724730
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.81454315
Short name T17
Test name
Test status
Simulation time 34973790 ps
CPU time 0.72 seconds
Started Apr 23 03:16:22 PM PDT 24
Finished Apr 23 03:16:24 PM PDT 24
Peak memory 205444 kb
Host smart-221b4bcd-891e-45e0-91e7-79639268227a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81454315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.81454315
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3741900051
Short name T557
Test name
Test status
Simulation time 83450723 ps
CPU time 0.86 seconds
Started Apr 23 03:16:09 PM PDT 24
Finished Apr 23 03:16:10 PM PDT 24
Peak memory 207160 kb
Host smart-f4ea80ff-0580-43b7-b35f-318fc62d2939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741900051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3741900051
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1436827089
Short name T426
Test name
Test status
Simulation time 104068981 ps
CPU time 2.22 seconds
Started Apr 23 03:16:15 PM PDT 24
Finished Apr 23 03:16:18 PM PDT 24
Peak memory 219060 kb
Host smart-4cdefeee-fa5b-4e68-b70b-cf8c0c07e62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436827089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1436827089
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3788597593
Short name T342
Test name
Test status
Simulation time 575274738 ps
CPU time 4.48 seconds
Started Apr 23 03:16:12 PM PDT 24
Finished Apr 23 03:16:17 PM PDT 24
Peak memory 217368 kb
Host smart-4a57a607-bad3-41e5-a217-f064560056c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788597593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3788597593
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3823574598
Short name T448
Test name
Test status
Simulation time 933812481 ps
CPU time 13.33 seconds
Started Apr 23 03:16:22 PM PDT 24
Finished Apr 23 03:16:36 PM PDT 24
Peak memory 223548 kb
Host smart-65891e83-28ae-4656-b1c4-650db51c9166
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3823574598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3823574598
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.877618614
Short name T599
Test name
Test status
Simulation time 1721485170 ps
CPU time 4.62 seconds
Started Apr 23 03:16:12 PM PDT 24
Finished Apr 23 03:16:17 PM PDT 24
Peak memory 216824 kb
Host smart-5dcc4bce-46ab-4f42-b162-74134d469b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877618614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.877618614
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.879435352
Short name T393
Test name
Test status
Simulation time 112126023 ps
CPU time 1.93 seconds
Started Apr 23 03:16:12 PM PDT 24
Finished Apr 23 03:16:14 PM PDT 24
Peak memory 216844 kb
Host smart-09a60fd2-52e5-4aa6-a0b3-1548cb55a456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879435352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.879435352
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3118046483
Short name T600
Test name
Test status
Simulation time 168612999 ps
CPU time 0.83 seconds
Started Apr 23 03:16:13 PM PDT 24
Finished Apr 23 03:16:14 PM PDT 24
Peak memory 206308 kb
Host smart-5b1c9e5c-7bd0-4343-ac4c-619ab8004184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118046483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3118046483
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3298728396
Short name T220
Test name
Test status
Simulation time 78128391 ps
CPU time 2.97 seconds
Started Apr 23 03:16:19 PM PDT 24
Finished Apr 23 03:16:22 PM PDT 24
Peak memory 222448 kb
Host smart-c7552594-9708-4b25-a860-c37f48160c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298728396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3298728396
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1593894670
Short name T626
Test name
Test status
Simulation time 18186081 ps
CPU time 0.68 seconds
Started Apr 23 03:16:42 PM PDT 24
Finished Apr 23 03:16:43 PM PDT 24
Peak memory 206300 kb
Host smart-d5a0d314-73f2-43c5-ab42-34580828dc3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593894670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
593894670
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1209748796
Short name T555
Test name
Test status
Simulation time 30802049 ps
CPU time 0.77 seconds
Started Apr 23 03:16:24 PM PDT 24
Finished Apr 23 03:16:25 PM PDT 24
Peak memory 207160 kb
Host smart-7bf70be1-d147-470a-97d5-483d4051cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209748796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1209748796
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1663437379
Short name T360
Test name
Test status
Simulation time 7578105233 ps
CPU time 16.77 seconds
Started Apr 23 03:16:33 PM PDT 24
Finished Apr 23 03:16:50 PM PDT 24
Peak memory 224084 kb
Host smart-c302272c-3457-457c-ab0f-eaee3258739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663437379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1663437379
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.391852760
Short name T208
Test name
Test status
Simulation time 1012869775 ps
CPU time 20.09 seconds
Started Apr 23 03:16:32 PM PDT 24
Finished Apr 23 03:16:53 PM PDT 24
Peak memory 241360 kb
Host smart-2f7edac0-b195-4453-b148-3010c0bf3a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391852760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.391852760
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.272347937
Short name T516
Test name
Test status
Simulation time 396016025 ps
CPU time 6.3 seconds
Started Apr 23 03:16:40 PM PDT 24
Finished Apr 23 03:16:47 PM PDT 24
Peak memory 223016 kb
Host smart-af8d39ff-dd2b-474b-98a5-25dbdf5f1417
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=272347937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.272347937
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1296511242
Short name T377
Test name
Test status
Simulation time 63012084209 ps
CPU time 68.37 seconds
Started Apr 23 03:16:26 PM PDT 24
Finished Apr 23 03:17:34 PM PDT 24
Peak memory 216860 kb
Host smart-ab4d484d-a924-439e-99a1-ec2686d37abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296511242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1296511242
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2525626536
Short name T705
Test name
Test status
Simulation time 3526441441 ps
CPU time 14.63 seconds
Started Apr 23 03:16:28 PM PDT 24
Finished Apr 23 03:16:43 PM PDT 24
Peak memory 216816 kb
Host smart-1b9f6d12-aed9-44ff-8972-997f5173039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525626536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2525626536
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3511821864
Short name T654
Test name
Test status
Simulation time 60250857 ps
CPU time 1.61 seconds
Started Apr 23 03:16:29 PM PDT 24
Finished Apr 23 03:16:31 PM PDT 24
Peak memory 208616 kb
Host smart-e565cd5b-a252-4f02-a01b-e952879b6baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511821864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3511821864
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2509178232
Short name T562
Test name
Test status
Simulation time 13022911 ps
CPU time 0.75 seconds
Started Apr 23 03:16:29 PM PDT 24
Finished Apr 23 03:16:30 PM PDT 24
Peak memory 206328 kb
Host smart-7e67becd-c72c-4e7e-b4d7-141c12ac6936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509178232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2509178232
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3961483115
Short name T276
Test name
Test status
Simulation time 18937717094 ps
CPU time 15.51 seconds
Started Apr 23 03:16:32 PM PDT 24
Finished Apr 23 03:16:48 PM PDT 24
Peak memory 223704 kb
Host smart-7b4c0844-a5b2-4285-be38-7faad16c1040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961483115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3961483115
Directory /workspace/9.spi_device_upload/latest
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