Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287077	1			T1	1		T2	1		T3	1
all_values[1]	287077	1			T1	1		T2	1		T3	1
all_values[2]	287077	1			T1	1		T2	1		T3	1
all_values[3]	287077	1			T1	1		T2	1		T3	1
all_values[4]	287077	1			T1	1		T2	1		T3	1
all_values[5]	287077	1			T1	1		T2	1		T3	1
all_values[6]	287077	1			T1	1		T2	1		T3	1
all_values[7]	287077	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294038

1

T1

8

T2

8

T3

8

auto[1]

2578

1

T21

75

T34

24

T39

101

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294338

1

T1

8

T2

8

T3

8

auto[1]

2278

1

T21

48

T19

11

T34

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	286649	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	115	1			T39	7		T49	6		T344	2
all_values[0]	auto[1]	auto[0]	188	1			T21	9		T34	2		T39	5
all_values[0]	auto[1]	auto[1]	125	1			T21	6		T39	2		T49	2
all_values[1]	auto[0]	auto[0]	286643	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	112	1			T21	4		T34	2		T39	1
all_values[1]	auto[1]	auto[0]	176	1			T21	8		T34	2		T39	9
all_values[1]	auto[1]	auto[1]	146	1			T21	3		T39	2		T40	2
all_values[2]	auto[0]	auto[0]	286653	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	111	1			T21	2		T34	1		T39	2
all_values[2]	auto[1]	auto[0]	171	1			T21	2		T34	2		T39	10
all_values[2]	auto[1]	auto[1]	142	1			T21	5		T34	1		T39	6
all_values[3]	auto[0]	auto[0]	286603	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	140	1			T21	4		T34	2		T39	4
all_values[3]	auto[1]	auto[0]	217	1			T21	10		T34	2		T39	8
all_values[3]	auto[1]	auto[1]	117	1			T34	4		T39	10		T49	4
all_values[4]	auto[0]	auto[0]	286613	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	155	1			T21	4		T39	3		T49	1
all_values[4]	auto[1]	auto[0]	185	1			T21	1		T34	1		T39	8
all_values[4]	auto[1]	auto[1]	124	1			T21	3		T39	3		T49	3
all_values[5]	auto[0]	auto[0]	286428	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	363	1			T21	6		T19	11		T34	3
all_values[5]	auto[1]	auto[0]	168	1			T21	8		T34	2		T39	9
all_values[5]	auto[1]	auto[1]	118	1			T21	1		T39	5		T40	2
all_values[6]	auto[0]	auto[0]	286611	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	110	1			T21	4		T39	5		T49	3
all_values[6]	auto[1]	auto[0]	215	1			T21	9		T34	2		T39	4
all_values[6]	auto[1]	auto[1]	141	1			T21	3		T39	11		T49	3
all_values[7]	auto[0]	auto[0]	286612	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	120	1			T34	1		T39	6		T40	1
all_values[7]	auto[1]	auto[0]	206	1			T21	4		T34	5		T39	7
all_values[7]	auto[1]	auto[1]	139	1			T21	3		T34	1		T39	2