Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	32	52	61.90

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1114	1			T1	10		T2	4		T4	10
auto[SpiFlashAddrCfg]	900	1			T1	12		T2	10		T4	4
auto[SpiFlashAddr3b]	1217	1			T1	2		T2	8		T5	4
auto[SpiFlashAddr4b]	848	1			T2	4		T4	4		T5	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3121

1

T1

24

T5

28

T7

8

auto[1]

958

1

T2

26

T4

18

T6

10

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2135

1

T1

16

T2

20

T4

4

auto[1]

1944

1

T1

8

T2

6

T4

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1601	1			T1	14		T2	14		T4	10
values[1]	87	1			T72	6		T107	2		T68	2
values[2]	250	1			T5	4		T6	4		T9	6
values[3]	174	1			T6	2		T10	2		T67	2
values[4]	187	1			T4	2		T8	2		T9	2
values[5]	206	1			T7	4		T87	3		T72	2
values[6]	150	1			T2	4		T67	4		T167	2
values[7]	172	1			T89	4		T107	4		T67	4
values[8]	1252	1			T1	10		T2	8		T4	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3478

1

T1

24

T2

26

T4

18

auto[1]

601

1

T87

13

T89

13

T275

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3963

1

T1

24

T2

26

T4

18

write

116

1

T66

2

T67

4

T68

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1921

1

T1

10

T2

6

T4

6

valids[0x1]

2158

1

T1

14

T2

20

T4

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	186	1			T1	8		T5	6		T67	2
internal_process_ops[0x5a]	208	1			T2	2		T5	4		T9	4
internal_process_ops[0x05]	222	1			T2	2		T4	2		T9	2
internal_process_ops[0x35]	198	1			T1	2		T2	2		T4	8
internal_process_ops[0x15]	196	1			T5	4		T72	2		T167	6
internal_process_ops[0x03]	288	1			T1	2		T2	10		T4	2
internal_process_ops[0x0b]	268	1			T87	5		T167	2		T116	2
internal_process_ops[0x3b]	320	1			T1	6		T5	2		T7	4
internal_process_ops[0x6b]	295	1			T6	2		T7	4		T8	2
internal_process_ops[0xbb]	289	1			T4	2		T87	5		T89	4
internal_process_ops[0xeb]	261	1			T4	2		T5	4		T87	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4043

1

T1

24

T2

26

T4

18

auto[1]

36

1

T67

4

T69

2

T70

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4079

1

T1

24

T2

26

T4

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled] , auto[SpiFlashAddrCfg]]	*	*	--	--	8
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[1]]	*	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddr4b]]	*	*	--	--	4

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

860

1

T1

10

T5

16

T9

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

220

1

T2

4

T4

10

T6

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

444

1

T1

12

T5

2

T9

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

224

1

T2

10

T4

4

T6

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

706

1

T1

2

T5

4

T8

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

292

1

T2

8

T6

2

T107

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

432

1

T5

6

T7

8

T10

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

186

1

T2

4

T4

4

T6

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T238

2

T223

2

T276

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

18

1

T67

4

T69

2

T70

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

26

1

T66

2

T277

4

T196

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

8

1

T77

2

T80

4

T260

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

14

1

T68

2

T31

2

T232

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

6

1

T78

4

T175

2

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

22

1

T71

2

T225

2

T261

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

4

1

T54

2

T79

2

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

198

1

T87

5

T275

10

T90

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

197

1

T87

8

T89

4

T90

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

204

1

T89

9

T275

3

T278

11

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2

1

T279

2

-

-

-

-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[4]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	288	1			T9	2		T72	2		T67	4
auto[0]	values[0]	valids[0x1]	1238	1			T1	14		T2	14		T4	10
auto[0]	values[1]	valids[0x1]	76	1			T72	6		T107	2		T68	2
auto[0]	values[2]	valids[0x0]	126	1			T6	4		T107	2		T166	8
auto[0]	values[2]	valids[0x1]	62	1			T5	4		T9	6		T168	2
auto[0]	values[3]	valids[0x0]	112	1			T6	2		T67	2		T116	10
auto[0]	values[3]	valids[0x1]	42	1			T10	2		T42	2		T180	2
auto[0]	values[4]	valids[0x0]	118	1			T8	2		T107	6		T73	6
auto[0]	values[4]	valids[0x1]	36	1			T4	2		T9	2		T168	2
auto[0]	values[5]	valids[0x0]	84	1			T7	4		T67	4		T73	2
auto[0]	values[5]	valids[0x1]	76	1			T72	2		T94	2		T195	6
auto[0]	values[6]	valids[0x0]	60	1			T67	4		T167	2		T261	2
auto[0]	values[6]	valids[0x1]	40	1			T2	4		T202	2		T264	10
auto[0]	values[7]	valids[0x0]	86	1			T107	4		T67	2		T83	2
auto[0]	values[7]	valids[0x1]	32	1			T67	2		T94	2		T174	4
auto[0]	values[8]	valids[0x0]	648	1			T1	10		T2	6		T4	6
auto[0]	values[8]	valids[0x1]	354	1			T2	2		T9	4		T107	6
auto[1]	values[0]	valids[0x1]	75	1			T87	5		T275	4		T279	2
auto[1]	values[1]	valids[0x1]	11	1			T279	7		T280	4		-	-
auto[1]	values[2]	valids[0x0]	45	1			T90	3		T281	5		T282	3
auto[1]	values[2]	valids[0x1]	17	1			T90	8		T283	2		T284	7
auto[1]	values[3]	valids[0x0]	10	1			T285	6		T286	4		-	-
auto[1]	values[3]	valids[0x1]	10	1			T287	6		T286	4		-	-
auto[1]	values[4]	valids[0x0]	33	1			T288	1		T289	7		T290	3
auto[1]	values[5]	valids[0x0]	27	1			T87	3		T281	3		T291	3
auto[1]	values[5]	valids[0x1]	19	1			T279	7		T103	5		T292	7
auto[1]	values[6]	valids[0x0]	42	1			T275	6		T278	3		T103	8
auto[1]	values[6]	valids[0x1]	8	1			T293	4		T294	4		-	-
auto[1]	values[7]	valids[0x0]	44	1			T89	4		T90	5		T290	5
auto[1]	values[7]	valids[0x1]	10	1			T295	4		T285	4		T296	2
auto[1]	values[8]	valids[0x0]	198	1			T87	5		T89	9		T275	3
auto[1]	values[8]	valids[0x1]	52	1			T297	7		T298	9		T289	4