Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
36.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	2	14	87.50
Crosses	72	54	18	25.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	1	1	50.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	48	16	25.00	100	1	1	0
cr_busyXwelXcsb	8	6	2	25.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_busy_bit

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1565582

1

T1

1

T2

1

T4

1

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1441506

1

T1

1

T2

1

T4

1

auto[1]

124076

1

T5

3090

T9

1536

T42

768

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	316774	1			T1	1		T2	1		T4	1
auto[524288:1048575]	134158	1			T5	75		T8	3657		T87	221
auto[1048576:1572863]	154290	1			T5	717		T7	23		T87	184
auto[1572864:2097151]	182659	1			T5	72		T7	68		T8	90
auto[2097152:2621439]	219399	1			T5	118		T7	21		T8	6
auto[2621440:3145727]	194613	1			T5	726		T7	1		T8	2
auto[3145728:3670015]	167134	1			T5	109		T87	1120		T89	75
auto[3670016:4194303]	196555	1			T7	4		T87	817		T89	36

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137332

1

T1

1

T2

1

T4

1

auto[1]

1428250

1

T5

642

T7

614

T8

7272

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_wel_bit

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1565582

1

T1

1

T2

1

T4

1

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	48	16	25.00	48

Automatically Generated Cross Bins for cr_all_except_csb

Element holes

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	*	--	--	16
[auto[1]]	*	*	*	--	--	32

Covered bins

cp_busy_bit

cp_wel_bit

cp_other_status

cp_is_host_read

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0:524287]

auto[0]

234449

1

T1

1

T2

1

T4

1

auto[0]

auto[0]

auto[0:524287]

auto[1]

82325

1

T5

2014

T9

1536

T42

633

auto[0]

auto[0]

auto[524288:1048575]

auto[0]

133078

1

T5

75

T8

3657

T87

221

auto[0]

auto[0]

auto[524288:1048575]

auto[1]

1080

1

T163

109

T164

245

T165

134

auto[0]

auto[0]

auto[1048576:1572863]

auto[0]

152912

1

T5

197

T7

23

T87

184

auto[0]

auto[0]

auto[1048576:1572863]

auto[1]

1378

1

T5

520

T42

4

T163

31

auto[0]

auto[0]

auto[1572864:2097151]

auto[0]

179232

1

T5

72

T7

68

T8

90

auto[0]

auto[0]

auto[1572864:2097151]

auto[1]

3427

1

T42

45

T43

6

T165

1

auto[0]

auto[0]

auto[2097152:2621439]

auto[0]

205250

1

T5

99

T7

21

T8

6

auto[0]

auto[0]

auto[2097152:2621439]

auto[1]

14149

1

T5

19

T164

588

T165

128

auto[0]

auto[0]

auto[2621440:3145727]

auto[0]

184623

1

T5

189

T7

1

T8

2

auto[0]

auto[0]

auto[2621440:3145727]

auto[1]

9990

1

T5

537

T163

116

T164

8

auto[0]

auto[0]

auto[3145728:3670015]

auto[0]

161484

1

T5

109

T87

1120

T89

75

auto[0]

auto[0]

auto[3145728:3670015]

auto[1]

5650

1

T42

55

T164

538

T43

497

auto[0]

auto[0]

auto[3670016:4194303]

auto[0]

190478

1

T7

4

T87

817

T89

36

auto[0]

auto[0]

auto[3670016:4194303]

auto[1]

6077

1

T42

31

T164

92

T43

513

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	6	2	25.00	6

Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	*	*	--	--	4

Covered bins

cp_busy_bit

cp_wel_bit

cp_sw_read_while_csb_active

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

137332

1

T1

1

T2

1

T4

1

auto[0]

auto[0]

auto[1]

1428250

1

T5

642

T7

614

T8

7272