Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	33	95	74.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	33	95	74.22	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2520

1

T1

24

T5

28

T7

8

auto[1]

958

1

T2

26

T4

18

T6

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	234	1			T6	10		T74	4		T31	14
values[1]	488	1			T71	6		T42	10		T94	32
values[2]	556	1			T2	26		T8	4		T68	18
values[3]	600	1			T107	30		T116	20		T27	4
values[4]	378	1			T9	22		T10	12		T66	4
values[5]	496	1			T1	24		T4	18		T299	2
values[6]	364	1			T7	8		T69	20		T257	2
values[7]	362	1			T5	28		T83	2		T230	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	396	1			T1	24		T6	10		T9	22
values[1]	288	1			T7	8		T83	2		T73	14
values[2]	484	1			T8	4		T10	12		T68	18
values[3]	464	1			T167	12		T69	20		T94	32
values[4]	474	1			T4	18		T107	30		T67	34
values[5]	566	1			T2	26		T5	28		T72	14
values[6]	336	1			T166	24		T169	10		T85	4
values[7]	470	1			T66	4		T30	6		T74	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	33	95	74.22	33

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[3]]	[values[3]]	0	1	1
[auto[0]]	[values[4]]	[values[1]]	0	1	1
[auto[0]]	[values[6]]	[values[6]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[0]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2]]	0	1	1
[auto[1]]	[values[1]]	[values[4]]	0	1	1
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[2]]	[values[4]]	0	1	1
[auto[1]]	[values[2]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[3]]	0	1	1
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[2]]	0	1	1
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[3]]	0	1	1
[auto[1]]	[values[5]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[6]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[6]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[7]]	[values[1]]	0	1	1
[auto[1]]	[values[7]]	[values[4]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	2	1			T250	2		-	-		-	-
auto[0]	values[0]	values[1]	10	1			T170	2		T26	8		-	-
auto[0]	values[0]	values[2]	26	1			T222	6		T256	14		T300	6
auto[0]	values[0]	values[3]	24	1			T301	24		-	-		-	-
auto[0]	values[0]	values[4]	14	1			T174	6		T302	4		T228	4
auto[0]	values[0]	values[5]	52	1			T31	14		T196	30		T182	8
auto[0]	values[0]	values[6]	10	1			T303	10		-	-		-	-
auto[0]	values[0]	values[7]	62	1			T184	20		T205	12		T304	26
auto[0]	values[1]	values[0]	120	1			T42	10		T93	14		T168	20
auto[0]	values[1]	values[1]	6	1			T226	6		-	-		-	-
auto[0]	values[1]	values[2]	64	1			T71	6		T187	2		T113	26
auto[0]	values[1]	values[3]	46	1			T270	16		T234	18		T305	4
auto[0]	values[1]	values[4]	12	1			T50	2		T111	10		-	-
auto[0]	values[1]	values[5]	30	1			T206	14		T306	16		-	-
auto[0]	values[1]	values[6]	88	1			T166	24		T169	10		T307	30
auto[0]	values[1]	values[7]	28	1			T255	2		T177	26		-	-
auto[0]	values[2]	values[0]	58	1			T277	8		T112	24		T308	26
auto[0]	values[2]	values[1]	34	1			T240	8		T233	26		-	-
auto[0]	values[2]	values[2]	46	1			T8	4		T68	18		T227	14
auto[0]	values[2]	values[3]	26	1			T167	12		T211	14		-	-
auto[0]	values[2]	values[4]	26	1			T183	4		T261	20		T309	2
auto[0]	values[2]	values[5]	38	1			T202	12		T209	26		-	-
auto[0]	values[2]	values[6]	10	1			T85	4		T192	6		-	-
auto[0]	values[2]	values[7]	92	1			T193	2		T310	24		T218	14
auto[0]	values[3]	values[0]	38	1			T188	26		T311	12		-	-
auto[0]	values[3]	values[1]	34	1			T105	34		-	-		-	-
auto[0]	values[3]	values[2]	104	1			T116	20		T195	14		T312	18
auto[0]	values[3]	values[4]	76	1			T165	18		T245	20		T313	22
auto[0]	values[3]	values[5]	122	1			T27	4		T163	2		T232	26
auto[0]	values[3]	values[6]	58	1			T110	24		T314	28		T315	6
auto[0]	values[3]	values[7]	38	1			T316	28		T207	10		-	-
auto[0]	values[4]	values[0]	44	1			T9	22		T231	22		-	-
auto[0]	values[4]	values[2]	36	1			T10	12		T171	20		T317	4
auto[0]	values[4]	values[3]	6	1			T213	2		T191	4		-	-
auto[0]	values[4]	values[4]	32	1			T259	2		T318	8		T319	14
auto[0]	values[4]	values[5]	72	1			T72	14		T28	32		T276	26
auto[0]	values[4]	values[6]	34	1			T238	26		T320	8		-	-
auto[0]	values[4]	values[7]	20	1			T66	4		T30	6		T263	2
auto[0]	values[5]	values[0]	32	1			T1	24		T271	8		-	-
auto[0]	values[5]	values[1]	24	1			T321	24		-	-		-	-
auto[0]	values[5]	values[2]	68	1			T262	24		T322	10		T186	12
auto[0]	values[5]	values[3]	20	1			T181	2		T323	18		-	-
auto[0]	values[5]	values[4]	72	1			T299	2		T95	24		T252	30
auto[0]	values[5]	values[5]	22	1			T225	2		T324	20		-	-
auto[0]	values[5]	values[6]	24	1			T325	24		-	-		-	-
auto[0]	values[5]	values[7]	72	1			T197	28		T179	28		T190	16
auto[0]	values[6]	values[0]	8	1			T24	8		-	-		-	-
auto[0]	values[6]	values[1]	38	1			T7	8		T43	6		T326	24
auto[0]	values[6]	values[2]	30	1			T164	12		T29	4		T237	14
auto[0]	values[6]	values[3]	28	1			T257	2		T267	12		T224	14
auto[0]	values[6]	values[4]	48	1			T242	4		T185	6		T264	22
auto[0]	values[6]	values[5]	42	1			T236	6		T25	16		T327	20
auto[0]	values[6]	values[7]	100	1			T204	6		T194	28		T229	26
auto[0]	values[7]	values[0]	4	1			T253	4		-	-		-	-
auto[0]	values[7]	values[1]	28	1			T83	2		T201	10		T328	6
auto[0]	values[7]	values[2]	30	1			T210	6		T199	24		-	-
auto[0]	values[7]	values[3]	62	1			T230	20		T53	22		T329	18
auto[0]	values[7]	values[4]	42	1			T52	10		T239	10		T330	22
auto[0]	values[7]	values[5]	54	1			T5	28		T215	2		T272	24
auto[0]	values[7]	values[6]	18	1			T331	14		T332	4		-	-
auto[0]	values[7]	values[7]	16	1			T189	12		T244	4		-	-
auto[1]	values[0]	values[0]	10	1			T6	10		-	-		-	-
auto[1]	values[0]	values[3]	20	1			T333	20		-	-		-	-
auto[1]	values[0]	values[7]	4	1			T74	4		-	-		-	-
auto[1]	values[1]	values[1]	24	1			T73	14		T268	10		-	-
auto[1]	values[1]	values[3]	36	1			T94	32		T217	4		-	-
auto[1]	values[1]	values[5]	34	1			T54	18		T216	16		-	-
auto[1]	values[2]	values[0]	52	1			T78	38		T334	14		-	-
auto[1]	values[2]	values[1]	28	1			T243	28		-	-		-	-
auto[1]	values[2]	values[2]	12	1			T251	12		-	-		-	-
auto[1]	values[2]	values[3]	102	1			T180	14		T246	28		T175	26
auto[1]	values[2]	values[5]	32	1			T2	26		T77	6		-	-
auto[1]	values[3]	values[2]	30	1			T173	30		-	-		-	-
auto[1]	values[3]	values[4]	46	1			T107	30		T274	16		-	-
auto[1]	values[3]	values[5]	22	1			T335	22		-	-		-	-
auto[1]	values[3]	values[6]	32	1			T273	20		T208	12		-	-
auto[1]	values[4]	values[0]	4	1			T336	4		-	-		-	-
auto[1]	values[4]	values[1]	28	1			T235	28		-	-		-	-
auto[1]	values[4]	values[3]	36	1			T337	36		-	-		-	-
auto[1]	values[4]	values[4]	40	1			T67	34		T131	6		-	-
auto[1]	values[4]	values[6]	26	1			T338	26		-	-		-	-
auto[1]	values[5]	values[1]	34	1			T75	16		T76	18		-	-
auto[1]	values[5]	values[2]	34	1			T203	14		T198	14		T254	6
auto[1]	values[5]	values[4]	66	1			T4	18		T176	22		T339	26
auto[1]	values[5]	values[5]	28	1			T86	28		-	-		-	-
auto[1]	values[6]	values[0]	16	1			T269	16		-	-		-	-
auto[1]	values[6]	values[3]	20	1			T69	20		-	-		-	-
auto[1]	values[6]	values[6]	24	1			T340	24		-	-		-	-
auto[1]	values[6]	values[7]	10	1			T70	10		-	-		-	-
auto[1]	values[7]	values[0]	8	1			T266	8		-	-		-	-
auto[1]	values[7]	values[2]	4	1			T341	4		-	-		-	-
auto[1]	values[7]	values[3]	38	1			T260	38		-	-		-	-
auto[1]	values[7]	values[5]	18	1			T79	18		-	-		-	-
auto[1]	values[7]	values[6]	12	1			T342	12		-	-		-	-
auto[1]	values[7]	values[7]	28	1			T80	28		-	-		-	-