Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1739

1

T1

12

T2

13

T4

9

auto[1]

2340

1

T1

12

T2

13

T4

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	316	1			T1	4		T2	10		T4	2
auto[4:7]	268	1			T2	2		T4	2		T9	2
auto[8:11]	290	1			T9	2		T87	5		T66	2
auto[12:15]	22	1			T261	2		T262	2		T327	2
auto[16:19]	24	1			T166	4		T76	2		T188	2
auto[20:23]	236	1			T5	4		T72	2		T167	6
auto[24:27]	36	1			T28	2		T316	2		T246	2
auto[28:31]	10	1			T72	6		T202	2		T319	2
auto[32:35]	18	1			T67	2		T68	2		T166	2
auto[36:39]	24	1			T9	2		T70	4		T262	2
auto[40:43]	14	1			T67	2		T74	2		T200	6
auto[44:47]	10	1			T131	2		T202	2		T80	2
auto[48:51]	38	1			T28	2		T171	4		T238	2
auto[52:55]	212	1			T1	2		T2	2		T4	8
auto[56:59]	330	1			T1	6		T5	2		T7	4
auto[60:63]	12	1			T71	2		T94	2		T231	2
auto[64:67]	16	1			T69	4		T173	2		T316	4
auto[68:71]	10	1			T67	2		T179	2		T200	6
auto[72:75]	24	1			T169	2		T195	2		T238	2
auto[76:79]	6	1			T229	2		T325	2		T301	2
auto[80:83]	18	1			T107	6		T74	2		T262	2
auto[84:87]	6	1			T10	2		T194	2		T301	2
auto[88:91]	222	1			T1	2		T2	2		T5	4
auto[92:95]	22	1			T168	2		T173	8		T264	2
auto[96:99]	6	1			T234	2		T336	2		T338	2
auto[100:103]	10	1			T266	2		T314	2		T272	4
auto[104:107]	311	1			T6	2		T7	4		T8	2
auto[108:111]	18	1			T28	6		T70	2		T327	2
auto[112:115]	26	1			T222	2		T174	4		T261	4
auto[116:119]	14	1			T253	2		T301	4		T313	6
auto[120:123]	16	1			T31	2		T222	2		T202	2
auto[124:127]	28	1			T180	4		T75	2		T203	4
auto[128:131]	22	1			T4	2		T67	6		T306	4
auto[132:135]	22	1			T107	2		T67	2		T68	2
auto[136:139]	8	1			T175	4		T325	2		T209	2
auto[140:143]	26	1			T10	2		T54	2		T266	2
auto[144:147]	22	1			T68	6		T94	2		T232	2
auto[148:151]	34	1			T166	8		T76	2		T238	4
auto[152:155]	6	1			T340	4		T178	2		-	-
auto[156:159]	202	1			T1	8		T5	6		T67	2
auto[160:163]	26	1			T168	2		T270	4		T189	2
auto[164:167]	26	1			T70	2		T253	2		T180	2
auto[168:171]	20	1			T225	2		T196	4		T252	2
auto[172:175]	16	1			T9	4		T69	2		T171	2
auto[176:179]	18	1			T238	2		T355	4		T176	2
auto[180:183]	82	1			T107	2		T27	4		T69	2
auto[184:187]	319	1			T4	2		T9	6		T87	5
auto[188:191]	8	1			T10	4		T238	2		T79	2
auto[192:195]	30	1			T67	4		T76	4		T270	4
auto[196:199]	6	1			T223	4		T273	2		-	-
auto[200:203]	14	1			T107	2		T223	4		T337	2
auto[204:207]	12	1			T31	2		T171	2		T80	4
auto[208:211]	6	1			T196	4		T80	2		-	-
auto[212:215]	28	1			T2	4		T10	2		T168	4
auto[216:219]	28	1			T86	2		T264	4		T273	2
auto[220:223]	24	1			T2	6		T262	2		T327	2
auto[224:227]	6	1			T229	2		T80	4		-	-
auto[228:231]	14	1			T168	2		T171	2		T214	2
auto[232:235]	327	1			T4	2		T5	4		T87	3
auto[236:239]	38	1			T1	2		T6	4		T72	2
auto[240:243]	30	1			T69	2		T28	4		T236	2
auto[244:247]	6	1			T54	6		-	-		-	-
auto[248:251]	14	1			T72	2		T54	2		T196	2
auto[252:255]	26	1			T66	2		T67	2		T73	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	98	1			T1	2		T2	5		T4	1
auto[0:3]	auto[1]	218	1			T1	2		T2	5		T4	1
auto[4:7]	auto[0]	134	1			T2	1		T4	1		T9	1
auto[4:7]	auto[1]	134	1			T2	1		T4	1		T9	1
auto[8:11]	auto[0]	105	1			T9	1		T66	1		T68	1
auto[8:11]	auto[1]	185	1			T9	1		T87	5		T66	1
auto[12:15]	auto[0]	11	1			T261	1		T262	1		T327	1
auto[12:15]	auto[1]	11	1			T261	1		T262	1		T327	1
auto[16:19]	auto[0]	12	1			T166	2		T76	1		T188	1
auto[16:19]	auto[1]	12	1			T166	2		T76	1		T188	1
auto[20:23]	auto[0]	118	1			T5	2		T72	1		T167	3
auto[20:23]	auto[1]	118	1			T5	2		T72	1		T167	3
auto[24:27]	auto[0]	18	1			T28	1		T316	1		T246	1
auto[24:27]	auto[1]	18	1			T28	1		T316	1		T246	1
auto[28:31]	auto[0]	5	1			T72	3		T202	1		T319	1
auto[28:31]	auto[1]	5	1			T72	3		T202	1		T319	1
auto[32:35]	auto[0]	9	1			T67	1		T68	1		T166	1
auto[32:35]	auto[1]	9	1			T67	1		T68	1		T166	1
auto[36:39]	auto[0]	12	1			T9	1		T70	2		T262	1
auto[36:39]	auto[1]	12	1			T9	1		T70	2		T262	1
auto[40:43]	auto[0]	7	1			T67	1		T74	1		T200	3
auto[40:43]	auto[1]	7	1			T67	1		T74	1		T200	3
auto[44:47]	auto[0]	5	1			T131	1		T202	1		T80	1
auto[44:47]	auto[1]	5	1			T131	1		T202	1		T80	1
auto[48:51]	auto[0]	19	1			T28	1		T171	2		T238	1
auto[48:51]	auto[1]	19	1			T28	1		T171	2		T238	1
auto[52:55]	auto[0]	106	1			T1	1		T2	1		T4	4
auto[52:55]	auto[1]	106	1			T1	1		T2	1		T4	4
auto[56:59]	auto[0]	103	1			T1	3		T5	1		T7	2
auto[56:59]	auto[1]	227	1			T1	3		T5	1		T7	2
auto[60:63]	auto[0]	6	1			T71	1		T94	1		T231	1
auto[60:63]	auto[1]	6	1			T71	1		T94	1		T231	1
auto[64:67]	auto[0]	8	1			T69	2		T173	1		T316	2
auto[64:67]	auto[1]	8	1			T69	2		T173	1		T316	2
auto[68:71]	auto[0]	5	1			T67	1		T179	1		T200	3
auto[68:71]	auto[1]	5	1			T67	1		T179	1		T200	3
auto[72:75]	auto[0]	12	1			T169	1		T195	1		T238	1
auto[72:75]	auto[1]	12	1			T169	1		T195	1		T238	1
auto[76:79]	auto[0]	3	1			T229	1		T325	1		T301	1
auto[76:79]	auto[1]	3	1			T229	1		T325	1		T301	1
auto[80:83]	auto[0]	9	1			T107	3		T74	1		T262	1
auto[80:83]	auto[1]	9	1			T107	3		T74	1		T262	1
auto[84:87]	auto[0]	3	1			T10	1		T194	1		T301	1
auto[84:87]	auto[1]	3	1			T10	1		T194	1		T301	1
auto[88:91]	auto[0]	111	1			T1	1		T2	1		T5	2
auto[88:91]	auto[1]	111	1			T1	1		T2	1		T5	2
auto[92:95]	auto[0]	11	1			T168	1		T173	4		T264	1
auto[92:95]	auto[1]	11	1			T168	1		T173	4		T264	1
auto[96:99]	auto[0]	3	1			T234	1		T336	1		T338	1
auto[96:99]	auto[1]	3	1			T234	1		T336	1		T338	1
auto[100:103]	auto[0]	5	1			T266	1		T314	1		T272	2
auto[100:103]	auto[1]	5	1			T266	1		T314	1		T272	2
auto[104:107]	auto[0]	107	1			T6	1		T7	2		T8	1
auto[104:107]	auto[1]	204	1			T6	1		T7	2		T8	1
auto[108:111]	auto[0]	9	1			T28	3		T70	1		T327	1
auto[108:111]	auto[1]	9	1			T28	3		T70	1		T327	1
auto[112:115]	auto[0]	13	1			T222	1		T174	2		T261	2
auto[112:115]	auto[1]	13	1			T222	1		T174	2		T261	2
auto[116:119]	auto[0]	7	1			T253	1		T301	2		T313	3
auto[116:119]	auto[1]	7	1			T253	1		T301	2		T313	3
auto[120:123]	auto[0]	8	1			T31	1		T222	1		T202	1
auto[120:123]	auto[1]	8	1			T31	1		T222	1		T202	1
auto[124:127]	auto[0]	14	1			T180	2		T75	1		T203	2
auto[124:127]	auto[1]	14	1			T180	2		T75	1		T203	2
auto[128:131]	auto[0]	11	1			T4	1		T67	3		T306	2
auto[128:131]	auto[1]	11	1			T4	1		T67	3		T306	2
auto[132:135]	auto[0]	11	1			T107	1		T67	1		T68	1
auto[132:135]	auto[1]	11	1			T107	1		T67	1		T68	1
auto[136:139]	auto[0]	4	1			T175	2		T325	1		T209	1
auto[136:139]	auto[1]	4	1			T175	2		T325	1		T209	1
auto[140:143]	auto[0]	13	1			T10	1		T54	1		T266	1
auto[140:143]	auto[1]	13	1			T10	1		T54	1		T266	1
auto[144:147]	auto[0]	11	1			T68	3		T94	1		T232	1
auto[144:147]	auto[1]	11	1			T68	3		T94	1		T232	1
auto[148:151]	auto[0]	17	1			T166	4		T76	1		T238	2
auto[148:151]	auto[1]	17	1			T166	4		T76	1		T238	2
auto[152:155]	auto[0]	3	1			T340	2		T178	1		-	-
auto[152:155]	auto[1]	3	1			T340	2		T178	1		-	-
auto[156:159]	auto[0]	101	1			T1	4		T5	3		T67	1
auto[156:159]	auto[1]	101	1			T1	4		T5	3		T67	1
auto[160:163]	auto[0]	13	1			T168	1		T270	2		T189	1
auto[160:163]	auto[1]	13	1			T168	1		T270	2		T189	1
auto[164:167]	auto[0]	13	1			T70	1		T253	1		T180	1
auto[164:167]	auto[1]	13	1			T70	1		T253	1		T180	1
auto[168:171]	auto[0]	10	1			T225	1		T196	2		T252	1
auto[168:171]	auto[1]	10	1			T225	1		T196	2		T252	1
auto[172:175]	auto[0]	8	1			T9	2		T69	1		T171	1
auto[172:175]	auto[1]	8	1			T9	2		T69	1		T171	1
auto[176:179]	auto[0]	9	1			T238	1		T355	2		T176	1
auto[176:179]	auto[1]	9	1			T238	1		T355	2		T176	1
auto[180:183]	auto[0]	41	1			T107	1		T27	2		T69	1
auto[180:183]	auto[1]	41	1			T107	1		T27	2		T69	1
auto[184:187]	auto[0]	110	1			T4	1		T9	3		T67	2
auto[184:187]	auto[1]	209	1			T4	1		T9	3		T87	5
auto[188:191]	auto[0]	4	1			T10	2		T238	1		T79	1
auto[188:191]	auto[1]	4	1			T10	2		T238	1		T79	1
auto[192:195]	auto[0]	15	1			T67	2		T76	2		T270	2
auto[192:195]	auto[1]	15	1			T67	2		T76	2		T270	2
auto[196:199]	auto[0]	3	1			T223	2		T273	1		-	-
auto[196:199]	auto[1]	3	1			T223	2		T273	1		-	-
auto[200:203]	auto[0]	7	1			T107	1		T223	2		T337	1
auto[200:203]	auto[1]	7	1			T107	1		T223	2		T337	1
auto[204:207]	auto[0]	6	1			T31	1		T171	1		T80	2
auto[204:207]	auto[1]	6	1			T31	1		T171	1		T80	2
auto[208:211]	auto[0]	3	1			T196	2		T80	1		-	-
auto[208:211]	auto[1]	3	1			T196	2		T80	1		-	-
auto[212:215]	auto[0]	14	1			T2	2		T10	1		T168	2
auto[212:215]	auto[1]	14	1			T2	2		T10	1		T168	2
auto[216:219]	auto[0]	14	1			T86	1		T264	2		T273	1
auto[216:219]	auto[1]	14	1			T86	1		T264	2		T273	1
auto[220:223]	auto[0]	12	1			T2	3		T262	1		T327	1
auto[220:223]	auto[1]	12	1			T2	3		T262	1		T327	1
auto[224:227]	auto[0]	3	1			T229	1		T80	2		-	-
auto[224:227]	auto[1]	3	1			T229	1		T80	2		-	-
auto[228:231]	auto[0]	7	1			T168	1		T171	1		T214	1
auto[228:231]	auto[1]	7	1			T168	1		T171	1		T214	1
auto[232:235]	auto[0]	123	1			T4	1		T5	2		T107	2
auto[232:235]	auto[1]	204	1			T4	1		T5	2		T87	3
auto[236:239]	auto[0]	19	1			T1	1		T6	2		T72	1
auto[236:239]	auto[1]	19	1			T1	1		T6	2		T72	1
auto[240:243]	auto[0]	15	1			T69	1		T28	2		T236	1
auto[240:243]	auto[1]	15	1			T69	1		T28	2		T236	1
auto[244:247]	auto[0]	3	1			T54	3		-	-		-	-
auto[244:247]	auto[1]	3	1			T54	3		-	-		-	-
auto[248:251]	auto[0]	7	1			T72	1		T54	1		T196	1
auto[248:251]	auto[1]	7	1			T72	1		T54	1		T196	1
auto[252:255]	auto[0]	13	1			T66	1		T67	1		T73	1
auto[252:255]	auto[1]	13	1			T66	1		T67	1		T73	1