Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	64	1			T116	2		T299	2		T50	2
auto[ReadAddrCrossIntoMailbox]	36	1			T52	2		T177	6		T249	2
auto[ReadAddrCrossOutOfMailbox]	48	1			T7	2		T116	4		T177	4
auto[ReadAddrCrossAllMailbox]	62	1			T7	2		T116	12		T52	2
auto[ReadAddrOutsideMailbox]	884	1			T1	8		T2	10		T4	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

547

1

T1

4

T2

5

T4

3

auto[1]

547

1

T1

4

T2

5

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	168	1			T1	2		T2	10		T4	2
read_ops[0x0b]	186	1			T167	2		T116	2		T94	2
read_ops[0x3b]	194	1			T1	6		T5	2		T7	4
read_ops[0x6b]	194	1			T6	2		T7	4		T8	2
read_ops[0xbb]	184	1			T4	2		T67	4		T68	2
read_ops[0xeb]	168	1			T4	2		T5	4		T107	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T299	1		T85	1		T165	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T299	1		T85	1		T165	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T249	1		T197	1		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T249	1		T197	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T312	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T312	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T267	2		T312	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T267	2		T312	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T1	1		T2	5		T4	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	72	1			T1	1		T2	5		T4	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T50	1		T177	1		T165	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T50	1		T177	1		T165	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T52	1		T307	2		T352	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T52	1		T307	2		T352	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T324	1		T211	1		T352	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T324	1		T211	1		T352	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T116	1		T52	1		T197	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T116	1		T52	1		T197	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	70	1			T167	1		T94	1		T168	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T167	1		T94	1		T168	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	2	1			T105	1		T241	1		-	-
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	2	1			T105	1		T241	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T105	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T105	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T7	1		T249	2		T105	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T7	1		T249	2		T105	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T249	1		T105	3		T307	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T249	1		T105	3		T307	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	83	1			T1	3		T5	1		T7	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	83	1			T1	3		T5	1		T7	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T177	2		T307	2		T197	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T177	2		T307	2		T197	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	9	1			T177	3		T324	2		T197	4
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	9	1			T177	3		T324	2		T197	4
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T116	1		T249	2		T307	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T116	1		T249	2		T307	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T7	1		T116	2		T307	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T7	1		T116	2		T307	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	70	1			T6	1		T7	1		T8	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T6	1		T7	1		T8	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	5	1			T165	3		T307	1		T221	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	5	1			T165	3		T307	1		T221	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T307	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T307	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T177	1		T307	1		T267	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T177	1		T307	1		T267	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T311	3		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T311	3		-	-		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	78	1			T4	1		T67	2		T68	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	78	1			T4	1		T67	2		T68	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T116	1		T85	1		T318	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T116	1		T85	1		T318	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T197	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T197	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T116	1		T177	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T116	1		T177	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T116	3		T177	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T116	3		T177	1		T197	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	69	1			T4	1		T5	2		T107	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	69	1			T4	1		T5	2		T107	2