Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	287077	1			T1	1		T2	1		T3	1
all_pins[1]	287077	1			T1	1		T2	1		T3	1
all_pins[2]	287077	1			T1	1		T2	1		T3	1
all_pins[3]	287077	1			T1	1		T2	1		T3	1
all_pins[4]	287077	1			T1	1		T2	1		T3	1
all_pins[5]	287077	1			T1	1		T2	1		T3	1
all_pins[6]	287077	1			T1	1		T2	1		T3	1
all_pins[7]	287077	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2295564	1			T1	8		T2	8		T3	8
values[0x1]	1052	1			T21	24		T34	6		T39	41
transitions[0x0=>0x1]	765	1			T21	19		T34	6		T39	32
transitions[0x1=>0x0]	777	1			T21	19		T34	6		T39	32

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286952	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	125	1			T21	6		T39	2		T49	2
all_pins[0]	transitions[0x0=>0x1]	94	1			T21	3		T39	2		T49	2
all_pins[0]	transitions[0x1=>0x0]	115	1			T39	2		T40	2		T49	4
all_pins[1]	values[0x0]	286931	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	146	1			T21	3		T39	2		T40	2
all_pins[1]	transitions[0x0=>0x1]	96	1			T21	2		T39	1		T40	2
all_pins[1]	transitions[0x1=>0x0]	92	1			T21	4		T34	1		T39	5
all_pins[2]	values[0x0]	286935	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	142	1			T21	5		T34	1		T39	6
all_pins[2]	transitions[0x0=>0x1]	114	1			T21	5		T34	1		T39	1
all_pins[2]	transitions[0x1=>0x0]	89	1			T34	4		T39	5		T49	4
all_pins[3]	values[0x0]	286960	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	117	1			T34	4		T39	10		T49	4
all_pins[3]	transitions[0x0=>0x1]	86	1			T34	4		T39	10		T49	4
all_pins[3]	transitions[0x1=>0x0]	93	1			T21	3		T39	3		T49	3
all_pins[4]	values[0x0]	286953	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	124	1			T21	3		T39	3		T49	3
all_pins[4]	transitions[0x0=>0x1]	96	1			T21	3		T39	3		T49	3
all_pins[4]	transitions[0x1=>0x0]	90	1			T21	1		T39	5		T40	2
all_pins[5]	values[0x0]	286959	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	118	1			T21	1		T39	5		T40	2
all_pins[5]	transitions[0x0=>0x1]	84	1			T21	1		T39	3		T40	2
all_pins[5]	transitions[0x1=>0x0]	107	1			T21	3		T39	9		T49	3
all_pins[6]	values[0x0]	286936	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	141	1			T21	3		T39	11		T49	3
all_pins[6]	transitions[0x0=>0x1]	104	1			T21	2		T39	10		T49	2
all_pins[6]	transitions[0x1=>0x0]	102	1			T21	2		T34	1		T39	1
all_pins[7]	values[0x0]	286938	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	139	1			T21	3		T34	1		T39	2
all_pins[7]	transitions[0x0=>0x1]	91	1			T21	3		T34	1		T39	2
all_pins[7]	transitions[0x1=>0x0]	89	1			T21	6		T39	2		T344	3