Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.01	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	54	74	57.81

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	54	74	57.81	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	570	1			T5	28		T6	10		T107	30
values[1]	306	1			T68	18		T166	24		T70	10
values[2]	386	1			T1	24		T167	12		T93	14
values[3]	394	1			T10	12		T66	4		T116	20
values[4]	450	1			T67	34		T74	4		T168	20
values[5]	584	1			T4	18		T7	8		T8	4
values[6]	354	1			T9	22		T69	20		T131	6
values[7]	434	1			T2	26		T71	6		T42	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	492	1			T5	28		T107	30		T83	2
values[1]	410	1			T7	8		T8	4		T71	6
values[2]	478	1			T10	12		T73	14		T163	2
values[3]	428	1			T67	34		T68	18		T27	4
values[4]	318	1			T2	26		T66	4		T131	6
values[5]	358	1			T168	20		T164	12		T169	10
values[6]	504	1			T1	24		T4	18		T6	10
values[7]	490	1			T167	12		T94	32		T31	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3442

1

T1

24

T2

26

T4

18

auto[1]

36

1

T67

4

T69

2

T70

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	54	74	57.81	54

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[values[0]]	0	1	1
[auto[0]]	[values[1]]	[values[5]]	0	1	1
[auto[0]]	[values[2]]	[values[4]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	7
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[1]]	0	1	1
[auto[1]]	[values[3]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[6]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	170	1			T5	28		T107	30		T75	14
auto[0]	values[0]	values[1]	22	1			T170	2		T171	20		-	-
auto[0]	values[0]	values[2]	24	1			T24	8		T172	16		-	-
auto[0]	values[0]	values[3]	114	1			T27	4		T173	30		T174	6
auto[0]	values[0]	values[4]	56	1			T52	10		T175	24		T176	22
auto[0]	values[0]	values[5]	36	1			T177	26		T178	10		-	-
auto[0]	values[0]	values[6]	74	1			T6	10		T76	16		T179	28
auto[0]	values[0]	values[7]	66	1			T180	14		T181	2		T182	8
auto[0]	values[1]	values[1]	80	1			T166	24		T183	4		T184	20
auto[0]	values[1]	values[2]	20	1			T185	6		T186	12		T187	2
auto[0]	values[1]	values[3]	44	1			T68	18		T188	26		-	-
auto[0]	values[1]	values[4]	32	1			T189	12		T190	16		T191	4
auto[0]	values[1]	values[6]	30	1			T95	24		T192	6		-	-
auto[0]	values[1]	values[7]	98	1			T70	8		T193	2		T194	28
auto[0]	values[2]	values[0]	70	1			T53	22		T195	14		T196	30
auto[0]	values[2]	values[1]	42	1			T197	28		T198	14		-	-
auto[0]	values[2]	values[2]	14	1			T93	14		-	-		-	-
auto[0]	values[2]	values[3]	76	1			T26	8		T199	24		T200	34
auto[0]	values[2]	values[5]	66	1			T43	6		T201	10		T202	12
auto[0]	values[2]	values[6]	84	1			T1	24		T203	14		T80	24
auto[0]	values[2]	values[7]	30	1			T167	12		T204	6		T205	12
auto[0]	values[3]	values[0]	30	1			T206	14		T207	10		T208	6
auto[0]	values[3]	values[1]	62	1			T116	20		T25	16		T209	26
auto[0]	values[3]	values[2]	176	1			T10	12		T163	2		T210	6
auto[0]	values[3]	values[3]	14	1			T211	14		-	-		-	-
auto[0]	values[3]	values[4]	18	1			T66	4		T212	14		-	-
auto[0]	values[3]	values[5]	38	1			T164	12		T213	2		T214	20
auto[0]	values[3]	values[6]	42	1			T110	24		T215	2		T216	16
auto[0]	values[3]	values[7]	4	1			T217	4		-	-		-	-
auto[0]	values[4]	values[0]	40	1			T218	14		T219	26		-	-
auto[0]	values[4]	values[1]	66	1			T86	28		T220	6		T221	8
auto[0]	values[4]	values[2]	48	1			T222	6		T223	28		T224	14
auto[0]	values[4]	values[3]	46	1			T67	30		T225	2		T226	6
auto[0]	values[4]	values[4]	22	1			T74	4		T227	14		T228	4
auto[0]	values[4]	values[5]	78	1			T168	20		T169	10		T229	26
auto[0]	values[4]	values[6]	92	1			T230	20		T231	22		T79	16
auto[0]	values[4]	values[7]	52	1			T232	26		T233	26		-	-
auto[0]	values[5]	values[0]	84	1			T83	2		T234	18		T235	28
auto[0]	values[5]	values[1]	60	1			T7	8		T8	4		T236	6
auto[0]	values[5]	values[2]	80	1			T73	14		T237	14		T238	26
auto[0]	values[5]	values[3]	30	1			T239	10		T240	8		T241	4
auto[0]	values[5]	values[4]	34	1			T242	4		T50	2		T243	28
auto[0]	values[5]	values[5]	108	1			T244	4		T245	20		T112	24
auto[0]	values[5]	values[6]	98	1			T4	18		T72	14		T30	6
auto[0]	values[5]	values[7]	90	1			T94	32		T31	14		T246	28
auto[0]	values[6]	values[0]	40	1			T247	10		T248	30		-	-
auto[0]	values[6]	values[1]	16	1			T249	16		-	-		-	-
auto[0]	values[6]	values[2]	42	1			T85	4		T250	2		T251	12
auto[0]	values[6]	values[3]	58	1			T69	18		T252	30		T106	10
auto[0]	values[6]	values[4]	108	1			T131	6		T253	4		T165	18
auto[0]	values[6]	values[5]	6	1			T254	6		-	-		-	-
auto[0]	values[6]	values[6]	26	1			T9	22		T77	4		-	-
auto[0]	values[6]	values[7]	54	1			T29	4		T255	2		T256	14
auto[0]	values[7]	values[0]	50	1			T42	10		T257	2		T258	22
auto[0]	values[7]	values[1]	60	1			T71	6		T259	2		T260	36
auto[0]	values[7]	values[2]	70	1			T261	20		T262	24		T263	2
auto[0]	values[7]	values[3]	38	1			T264	22		T265	16		-	-
auto[0]	values[7]	values[4]	46	1			T2	26		T266	8		T267	12
auto[0]	values[7]	values[5]	26	1			T268	10		T269	16		-	-
auto[0]	values[7]	values[6]	48	1			T270	16		T271	8		T272	24
auto[0]	values[7]	values[7]	94	1			T28	32		T273	20		T274	16
auto[1]	values[0]	values[0]	2	1			T75	2		-	-		-	-
auto[1]	values[0]	values[3]	2	1			T54	2		-	-		-	-
auto[1]	values[0]	values[4]	2	1			T175	2		-	-		-	-
auto[1]	values[0]	values[6]	2	1			T76	2		-	-		-	-
auto[1]	values[1]	values[7]	2	1			T70	2		-	-		-	-
auto[1]	values[2]	values[6]	4	1			T80	4		-	-		-	-
auto[1]	values[3]	values[0]	6	1			T208	6		-	-		-	-
auto[1]	values[3]	values[2]	4	1			T78	4		-	-		-	-
auto[1]	values[4]	values[3]	4	1			T67	4		-	-		-	-
auto[1]	values[4]	values[6]	2	1			T79	2		-	-		-	-
auto[1]	values[6]	values[3]	2	1			T69	2		-	-		-	-
auto[1]	values[6]	values[6]	2	1			T77	2		-	-		-	-
auto[1]	values[7]	values[1]	2	1			T260	2		-	-		-	-