Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1595

1

T12

6

T13

8

T14

15

auto[1]

1523

1

T12

2

T13

11

T14

14

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T12

8

T18

22

T58

24

auto[1]

2411

1

T13

19

T14

29

T15

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2831

1

T12

6

T13

19

T14

29

auto[1]

287

1

T12

2

T18

5

T58

10

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	599	1			T12	3		T13	4		T14	3
valid[1]	623	1			T13	4		T14	5		T15	2
valid[2]	661	1			T12	3		T13	5		T14	11
valid[3]	616	1			T12	1		T13	3		T14	4
valid[4]	619	1			T12	1		T13	3		T14	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	51	1			T12	1		T18	3		T61	1
auto[0]	auto[0]	valid[0]	auto[1]	223	1			T13	1		T14	3		T23	1
auto[0]	auto[0]	valid[1]	auto[0]	32	1			T18	1		T62	3		T366	1
auto[0]	auto[0]	valid[1]	auto[1]	248	1			T13	3		T14	3		T15	2
auto[0]	auto[0]	valid[2]	auto[0]	49	1			T12	3		T18	3		T58	1
auto[0]	auto[0]	valid[2]	auto[1]	268	1			T13	2		T14	4		T15	1
auto[0]	auto[0]	valid[3]	auto[0]	51	1			T12	1		T18	2		T58	1
auto[0]	auto[0]	valid[3]	auto[1]	236	1			T13	1		T14	3		T15	3
auto[0]	auto[0]	valid[4]	auto[0]	42	1			T18	3		T58	2		T62	1
auto[0]	auto[0]	valid[4]	auto[1]	249	1			T13	1		T14	2		T15	1
auto[0]	auto[1]	valid[0]	auto[0]	35	1			T12	1		T18	2		T58	2
auto[0]	auto[1]	valid[0]	auto[1]	223	1			T13	3		T15	4		T58	1
auto[0]	auto[1]	valid[1]	auto[0]	42	1			T18	1		T58	1		T60	2
auto[0]	auto[1]	valid[1]	auto[1]	239	1			T13	1		T14	2		T23	1
auto[0]	auto[1]	valid[2]	auto[0]	34	1			T58	3		T61	1		T101	1
auto[0]	auto[1]	valid[2]	auto[1]	254	1			T13	3		T14	7		T15	2
auto[0]	auto[1]	valid[3]	auto[0]	46	1			T58	2		T61	1		T101	3
auto[0]	auto[1]	valid[3]	auto[1]	243	1			T13	2		T14	1		T15	3
auto[0]	auto[1]	valid[4]	auto[0]	38	1			T18	2		T58	2		T62	2
auto[0]	auto[1]	valid[4]	auto[1]	228	1			T13	2		T14	4		T15	1
auto[1]	auto[0]	valid[0]	auto[0]	34	1			T58	1		T61	1		T62	1
auto[1]	auto[0]	valid[1]	auto[0]	22	1			T58	1		T101	1		T366	2
auto[1]	auto[0]	valid[2]	auto[0]	30	1			T18	1		T62	1		T101	1
auto[1]	auto[0]	valid[3]	auto[0]	27	1			T18	1		T58	1		T64	2
auto[1]	auto[0]	valid[4]	auto[0]	33	1			T12	1		T58	1		T62	1
auto[1]	auto[1]	valid[0]	auto[0]	33	1			T12	1		T18	1		T61	1
auto[1]	auto[1]	valid[1]	auto[0]	40	1			T18	1		T58	3		T64	1
auto[1]	auto[1]	valid[2]	auto[0]	26	1			T18	1		T61	2		T62	2
auto[1]	auto[1]	valid[3]	auto[0]	13	1			T58	2		T60	1		T61	1
auto[1]	auto[1]	valid[4]	auto[0]	29	1			T58	1		T60	2		T61	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal