Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19270

1

T12

186

T18

526

T19

12

auto[1]

24104

1

T13

19

T14

269

T15

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36131

1

T12

118

T13

19

T14

269

auto[1]

7243

1

T12

68

T18

156

T19

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	22314	1			T12	104		T13	19		T14	128
others[1]	3680	1			T12	14		T14	29		T18	41
others[2]	3634	1			T12	20		T14	26		T18	39
others[3]	4228	1			T12	19		T14	26		T18	56
interest[1]	2354	1			T12	7		T14	14		T18	30
interest[4]	14669	1			T12	73		T13	19		T14	89
interest[64]	7164	1			T12	22		T14	46		T18	85

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	6066	1			T12	67		T18	192		T19	3
auto[0]	auto[0]	others[1]	1069	1			T12	9		T18	26		T19	3
auto[0]	auto[0]	others[2]	1033	1			T12	14		T18	32		T58	39
auto[0]	auto[0]	others[3]	1184	1			T12	11		T18	37		T58	33
auto[0]	auto[0]	interest[1]	657	1			T12	5		T18	25		T58	19
auto[0]	auto[0]	interest[4]	3940	1			T12	47		T18	121		T58	143
auto[0]	auto[0]	interest[64]	2018	1			T12	12		T18	58		T58	51
auto[0]	auto[1]	others[0]	12561	1			T13	19		T14	128		T15	17
auto[0]	auto[1]	others[1]	2007	1			T14	29		T58	11		T59	57
auto[0]	auto[1]	others[2]	1991	1			T14	26		T58	4		T59	43
auto[0]	auto[1]	others[3]	2287	1			T14	26		T58	9		T59	48
auto[0]	auto[1]	interest[1]	1298	1			T14	14		T58	5		T59	28
auto[0]	auto[1]	interest[4]	8344	1			T13	19		T14	89		T15	17
auto[0]	auto[1]	interest[64]	3960	1			T14	46		T58	27		T59	96
auto[1]	auto[0]	others[0]	3687	1			T12	37		T18	83		T19	3
auto[1]	auto[0]	others[1]	604	1			T12	5		T18	15		T58	29
auto[1]	auto[0]	others[2]	610	1			T12	6		T18	7		T58	27
auto[1]	auto[0]	others[3]	757	1			T12	8		T18	19		T58	29
auto[1]	auto[0]	interest[1]	399	1			T12	2		T18	5		T19	1
auto[1]	auto[0]	interest[4]	2385	1			T12	26		T18	54		T19	3
auto[1]	auto[0]	interest[64]	1186	1			T12	10		T18	27		T19	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal