Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	535	1			T21	14		T34	7		T39	21
all_values[1]	535	1			T21	14		T34	7		T39	21
all_values[2]	535	1			T21	14		T34	7		T39	21
all_values[3]	535	1			T21	14		T34	7		T39	21
all_values[4]	535	1			T21	14		T34	7		T39	21
all_values[5]	535	1			T21	14		T34	7		T39	21
all_values[6]	535	1			T21	14		T34	7		T39	21
all_values[7]	535	1			T21	14		T34	7		T39	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2188

1

T21

55

T34

36

T39

86

auto[1]

2092

1

T21

57

T34

20

T39

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1717

1

T21

38

T34

24

T39

78

auto[1]

2563

1

T21

74

T34

32

T39

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2443

1

T21

56

T34

30

T39

106

auto[1]

1837

1

T21

56

T34

26

T39

62

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	115	1			T21	2		T34	4		T39	6
all_values[0]	auto[0]	auto[0]	auto[1]	46	1			T39	3		T49	3		T343	3
all_values[0]	auto[0]	auto[1]	auto[0]	93	1			T21	2		T34	1		T39	2
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T21	2		T39	1		T49	1
all_values[0]	auto[1]	auto[0]	auto[1]	114	1			T21	2		T34	1		T39	6
all_values[0]	auto[1]	auto[1]	auto[1]	115	1			T21	6		T34	1		T39	3
all_values[1]	auto[0]	auto[0]	auto[0]	105	1			T21	2		T34	2		T39	5
all_values[1]	auto[0]	auto[0]	auto[1]	51	1			T21	3		T34	1		T49	2
all_values[1]	auto[0]	auto[1]	auto[0]	87	1			T21	1		T39	7		T49	4
all_values[1]	auto[0]	auto[1]	auto[1]	60	1			T21	1		T40	1		T344	1
all_values[1]	auto[1]	auto[0]	auto[1]	114	1			T21	2		T34	2		T39	5
all_values[1]	auto[1]	auto[1]	auto[1]	118	1			T21	5		T34	2		T39	4
all_values[2]	auto[0]	auto[0]	auto[0]	109	1			T21	3		T34	1		T39	2
all_values[2]	auto[0]	auto[0]	auto[1]	49	1			T21	2		T39	2		T49	2
all_values[2]	auto[0]	auto[1]	auto[0]	98	1			T21	1		T39	8		T40	1
all_values[2]	auto[0]	auto[1]	auto[1]	50	1			T21	2		T39	1		T344	1
all_values[2]	auto[1]	auto[0]	auto[1]	110	1			T21	2		T34	3		T39	2
all_values[2]	auto[1]	auto[1]	auto[1]	119	1			T21	4		T34	3		T39	6
all_values[3]	auto[0]	auto[0]	auto[0]	111	1			T21	3		T39	1		T49	5
all_values[3]	auto[0]	auto[0]	auto[1]	42	1			T21	1		T34	2		T39	3
all_values[3]	auto[0]	auto[1]	auto[0]	110	1			T21	4		T39	5		T40	2
all_values[3]	auto[0]	auto[1]	auto[1]	49	1			T34	2		T39	3		T49	1
all_values[3]	auto[1]	auto[0]	auto[1]	119	1			T21	3		T34	1		T39	2
all_values[3]	auto[1]	auto[1]	auto[1]	104	1			T21	3		T34	2		T39	7
all_values[4]	auto[0]	auto[0]	auto[0]	112	1			T21	3		T34	4		T39	9
all_values[4]	auto[0]	auto[0]	auto[1]	63	1			T21	1		T39	2		T49	1
all_values[4]	auto[0]	auto[1]	auto[0]	82	1			T34	1		T39	3		T40	3
all_values[4]	auto[0]	auto[1]	auto[1]	51	1			T21	2		T39	1		T344	1
all_values[4]	auto[1]	auto[0]	auto[1]	125	1			T21	6		T34	2		T39	4
all_values[4]	auto[1]	auto[1]	auto[1]	102	1			T21	2		T39	2		T40	1
all_values[5]	auto[0]	auto[0]	auto[0]	176	1			T21	3		T34	2		T39	8
all_values[5]	auto[0]	auto[1]	auto[0]	121	1			T21	4		T34	2		T39	6
all_values[5]	auto[1]	auto[0]	auto[1]	125	1			T21	6		T34	3		T39	3
all_values[5]	auto[1]	auto[1]	auto[1]	113	1			T21	1		T39	4		T40	2
all_values[6]	auto[0]	auto[0]	auto[0]	92	1			T21	1		T34	2		T39	2
all_values[6]	auto[0]	auto[0]	auto[1]	43	1			T21	2		T39	2		T344	1
all_values[6]	auto[0]	auto[1]	auto[0]	109	1			T21	3		T34	1		T39	2
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T21	1		T39	6		T49	2
all_values[6]	auto[1]	auto[0]	auto[1]	109	1			T21	2		T34	3		T39	6
all_values[6]	auto[1]	auto[1]	auto[1]	120	1			T21	5		T34	1		T39	3
all_values[7]	auto[0]	auto[0]	auto[0]	97	1			T21	4		T34	2		T39	7
all_values[7]	auto[0]	auto[0]	auto[1]	50	1			T39	4		T40	1		T49	4
all_values[7]	auto[0]	auto[1]	auto[0]	100	1			T21	2		T34	2		T39	5
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T21	1		T34	1		T49	2
all_values[7]	auto[1]	auto[0]	auto[1]	111	1			T21	2		T34	1		T39	2
all_values[7]	auto[1]	auto[1]	auto[1]	119	1			T21	5		T34	1		T39	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal