Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	261921	1			T1	1		T2	1		T14	1
all_values[1]	261921	1			T1	1		T2	1		T14	1
all_values[2]	261921	1			T1	1		T2	1		T14	1
all_values[3]	261921	1			T1	1		T2	1		T14	1
all_values[4]	261921	1			T1	1		T2	1		T14	1
all_values[5]	261921	1			T1	1		T2	1		T14	1
all_values[6]	261921	1			T1	1		T2	1		T14	1
all_values[7]	261921	1			T1	1		T2	1		T14	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2092964

1

T1

8

T2

8

T14

8

auto[1]

2404

1

T31

43

T33

120

T39

85

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2093208

1

T1

8

T2

8

T14

8

auto[1]

2160

1

T13

4

T17

4

T18

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	261491	1			T1	1		T2	1		T14	1
all_values[0]	auto[0]	auto[1]	127	1			T31	2		T33	10		T39	4
all_values[0]	auto[1]	auto[0]	190	1			T31	1		T33	4		T39	5
all_values[0]	auto[1]	auto[1]	113	1			T31	1		T33	7		T39	6
all_values[1]	auto[0]	auto[0]	261518	1			T1	1		T2	1		T14	1
all_values[1]	auto[0]	auto[1]	127	1			T31	2		T33	8		T39	3
all_values[1]	auto[1]	auto[0]	164	1			T31	1		T33	10		T39	7
all_values[1]	auto[1]	auto[1]	112	1			T31	1		T33	4		T39	6
all_values[2]	auto[0]	auto[0]	261487	1			T1	1		T2	1		T14	1
all_values[2]	auto[0]	auto[1]	120	1			T31	1		T33	10		T39	2
all_values[2]	auto[1]	auto[0]	166	1			T31	3		T33	4		T39	6
all_values[2]	auto[1]	auto[1]	148	1			T31	3		T33	6		T39	8
all_values[3]	auto[0]	auto[0]	261502	1			T1	1		T2	1		T14	1
all_values[3]	auto[0]	auto[1]	142	1			T31	1		T33	6		T313	1
all_values[3]	auto[1]	auto[0]	192	1			T31	6		T33	7		T39	5
all_values[3]	auto[1]	auto[1]	85	1			T31	1		T33	6		T39	3
all_values[4]	auto[0]	auto[0]	261461	1			T1	1		T2	1		T14	1
all_values[4]	auto[0]	auto[1]	146	1			T159	2		T31	2		T33	9
all_values[4]	auto[1]	auto[0]	188	1			T31	6		T33	5		T39	8
all_values[4]	auto[1]	auto[1]	126	1			T31	2		T33	10		T39	6
all_values[5]	auto[0]	auto[0]	261271	1			T1	1		T2	1		T14	1
all_values[5]	auto[0]	auto[1]	339	1			T13	4		T17	4		T18	1
all_values[5]	auto[1]	auto[0]	215	1			T31	2		T33	21		T39	3
all_values[5]	auto[1]	auto[1]	96	1			T31	2		T33	4		T39	2
all_values[6]	auto[0]	auto[0]	261496	1			T1	1		T2	1		T14	1
all_values[6]	auto[0]	auto[1]	116	1			T31	1		T33	7		T39	2
all_values[6]	auto[1]	auto[0]	185	1			T31	5		T33	7		T39	8
all_values[6]	auto[1]	auto[1]	124	1			T31	1		T33	5		T39	4
all_values[7]	auto[0]	auto[0]	261493	1			T1	1		T2	1		T14	1
all_values[7]	auto[0]	auto[1]	128	1			T31	3		T33	7		T39	2
all_values[7]	auto[1]	auto[0]	189	1			T31	5		T33	10		T39	6
all_values[7]	auto[1]	auto[1]	111	1			T31	3		T33	10		T39	2