Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	32	52	61.90

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1114	1			T1	2		T2	6		T4	16
auto[SpiFlashAddrCfg]	878	1			T2	4		T4	6		T5	11
auto[SpiFlashAddr3b]	926	1			T1	2		T2	8		T4	6
auto[SpiFlashAddr4b]	808	1			T2	10		T4	6		T6	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2868

1

T1

4

T2

28

T5

13

auto[1]

858

1

T4

34

T9

16

T19

18

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1969

1

T1

4

T2

8

T4

16

auto[1]

1757

1

T2

20

T4

18

T5

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1470	1			T1	2		T2	4		T4	14
values[1]	121	1			T2	2		T9	4		T85	2
values[2]	174	1			T43	4		T73	2		T301	7
values[3]	192	1			T2	6		T7	12		T19	2
values[4]	180	1			T4	4		T7	4		T8	2
values[5]	185	1			T4	2		T6	8		T8	2
values[6]	158	1			T1	2		T2	4		T26	6
values[7]	159	1			T2	8		T4	2		T25	2
values[8]	1087	1			T2	4		T4	12		T5	11

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3224

1

T1

4

T2

28

T4

34

auto[1]

502

1

T5

13

T67

3

T83

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3602

1

T1

4

T2

28

T4

30

write

124

1

T4

4

T8

2

T19

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1703

1

T1

2

T2

20

T4

12

valids[0x1]

2023

1

T1

2

T2

8

T4

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	180	1			T2	2		T4	2		T25	8
internal_process_ops[0x5a]	184	1			T88	2		T43	2		T73	4
internal_process_ops[0x05]	228	1			T7	2		T8	2		T19	4
internal_process_ops[0x35]	200	1			T2	2		T93	14		T182	2
internal_process_ops[0x15]	172	1			T4	4		T9	4		T93	4
internal_process_ops[0x03]	260	1			T4	4		T6	8		T7	2
internal_process_ops[0x0b]	240	1			T4	2		T5	2		T8	2
internal_process_ops[0x3b]	263	1			T2	4		T4	2		T5	6
internal_process_ops[0x6b]	249	1			T2	2		T19	2		T26	6
internal_process_ops[0xbb]	249	1			T2	2		T4	2		T5	5
internal_process_ops[0xeb]	249	1			T2	6		T41	2		T159	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3688

1

T1

4

T2

28

T4

30

auto[1]

38

1

T4

4

T19

2

T68

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3726

1

T1

4

T2

28

T4

34

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

832

1

T1

2

T2

6

T7

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

234

1

T4

12

T9

8

T19

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

452

1

T2

4

T7

12

T8

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

214

1

T4

6

T9

8

T19

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

526

1

T1

2

T2

8

T6

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

200

1

T4

6

T19

8

T297

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

470

1

T2

10

T6

2

T7

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

172

1

T4

6

T182

2

T68

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

36

1

T93

14

T255

4

T302

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

12

1

T4

4

T74

2

T77

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

14

1

T72

2

T276

4

T288

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

10

1

T19

2

T73

8

-

-

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

18

1

T8

2

T186

2

T71

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

12

1

T68

4

T76

2

T79

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

18

1

T276

2

T264

2

T287

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

4

1

T75

2

T78

2

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

188

1

T5

11

T83

9

T84

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

170

1

T5

2

T67

3

T84

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

144

1

T83

3

T159

4

T303

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	270	1			T1	2		T4	2		T7	6
auto[0]	values[0]	valids[0x1]	1156	1			T2	4		T4	12		T7	6
auto[0]	values[1]	valids[0x1]	94	1			T2	2		T9	4		T85	2
auto[0]	values[2]	valids[0x0]	62	1			T73	2		T194	2		T74	2
auto[0]	values[2]	valids[0x1]	58	1			T43	4		T194	4		T69	2
auto[0]	values[3]	valids[0x0]	120	1			T2	6		T7	8		T19	2
auto[0]	values[3]	valids[0x1]	50	1			T7	4		T72	2		T182	2
auto[0]	values[4]	valids[0x0]	82	1			T4	4		T7	4		T25	8
auto[0]	values[4]	valids[0x1]	52	1			T8	2		T10	2		T26	2
auto[0]	values[5]	valids[0x0]	74	1			T4	2		T10	4		T25	4
auto[0]	values[5]	valids[0x1]	68	1			T6	8		T8	2		T73	2
auto[0]	values[6]	valids[0x0]	104	1			T2	4		T121	2		T68	2
auto[0]	values[6]	valids[0x1]	36	1			T1	2		T26	6		T72	2
auto[0]	values[7]	valids[0x0]	94	1			T2	6		T25	2		T182	2
auto[0]	values[7]	valids[0x1]	36	1			T2	2		T4	2		T88	2
auto[0]	values[8]	valids[0x0]	584	1			T2	4		T4	4		T6	2
auto[0]	values[8]	valids[0x1]	284	1			T4	8		T7	2		T8	4
auto[1]	values[0]	valids[0x1]	44	1			T5	2		T160	5		T304	3
auto[1]	values[1]	valids[0x1]	27	1			T303	4		T108	2		T305	5
auto[1]	values[2]	valids[0x0]	33	1			T301	7		T306	6		T307	3
auto[1]	values[2]	valids[0x1]	21	1			T308	12		T309	3		T310	6
auto[1]	values[3]	valids[0x0]	17	1			T84	5		T304	2		T311	2
auto[1]	values[3]	valids[0x1]	5	1			T312	5		-	-		-	-
auto[1]	values[4]	valids[0x0]	27	1			T83	2		T159	11		T306	2
auto[1]	values[4]	valids[0x1]	19	1			T83	7		T306	6		T309	6
auto[1]	values[5]	valids[0x0]	30	1			T303	4		T108	2		T313	5
auto[1]	values[5]	valids[0x1]	13	1			T307	7		T314	6		-	-
auto[1]	values[6]	valids[0x0]	16	1			T315	3		T316	6		T317	4
auto[1]	values[6]	valids[0x1]	2	1			T318	2		-	-		-	-
auto[1]	values[7]	valids[0x0]	11	1			T319	3		T320	4		T321	4
auto[1]	values[7]	valids[0x1]	18	1			T312	4		T322	8		T310	6
auto[1]	values[8]	valids[0x0]	179	1			T5	11		T84	3		T159	5
auto[1]	values[8]	valids[0x1]	40	1			T67	3		T83	3		T323	5