Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1382183 1 T1 144 T2 1 T4 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1252427 1 T1 144 T2 1 T4 1
auto[1] 129756 1 T8 512 T41 308 T26 1032


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 306298 1 T1 56 T2 1 T4 1
auto[524288:1048575] 155068 1 T5 6094 T6 2833 T67 309
auto[1048576:1572863] 130873 1 T1 46 T5 2589 T6 6863
auto[1572864:2097151] 178562 1 T5 28 T6 7744 T66 1
auto[2097152:2621439] 143588 1 T1 42 T5 1405 T6 2411
auto[2621440:3145727] 147328 1 T5 2771 T6 746 T67 197
auto[3145728:3670015] 161173 1 T5 56 T6 4596 T67 1
auto[3670016:4194303] 159293 1 T5 13131 T6 5744 T67 728


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 140971 1 T1 15 T2 1 T4 1
auto[1] 1241212 1 T1 129 T5 25830 T6 35794


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1382183 1 T1 144 T2 1 T4 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 216700 1 T1 56 T2 1 T4 1
auto[0] auto[0] auto[0:524287] auto[1] 89598 1 T8 512 T41 308 T26 1032
auto[0] auto[0] auto[524288:1048575] auto[0] 149877 1 T5 6094 T6 2833 T67 309
auto[0] auto[0] auto[524288:1048575] auto[1] 5191 1 T54 498 T92 39 T179 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 127762 1 T1 46 T5 2589 T6 6863
auto[0] auto[0] auto[1048576:1572863] auto[1] 3111 1 T54 42 T91 675 T180 354
auto[0] auto[0] auto[1572864:2097151] auto[0] 175968 1 T5 28 T6 7744 T66 1
auto[0] auto[0] auto[1572864:2097151] auto[1] 2594 1 T54 1757 T181 501 T91 1
auto[0] auto[0] auto[2097152:2621439] auto[0] 138208 1 T1 42 T5 1405 T6 2411
auto[0] auto[0] auto[2097152:2621439] auto[1] 5380 1 T93 258 T54 89 T92 3
auto[0] auto[0] auto[2621440:3145727] auto[0] 141228 1 T5 2771 T6 746 T67 197
auto[0] auto[0] auto[2621440:3145727] auto[1] 6100 1 T93 6002 T54 55 T180 35
auto[0] auto[0] auto[3145728:3670015] auto[0] 155223 1 T5 56 T6 4596 T67 1
auto[0] auto[0] auto[3145728:3670015] auto[1] 5950 1 T93 8 T54 2 T91 1
auto[0] auto[0] auto[3670016:4194303] auto[0] 147461 1 T5 13131 T6 5744 T67 728
auto[0] auto[0] auto[3670016:4194303] auto[1] 11832 1 T93 6295 T54 2531 T181 16


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 140971 1 T1 15 T2 1 T4 1
auto[0] auto[0] auto[1] 1241212 1 T1 129 T5 25830 T6 35794

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