Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	29	99	77.34

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	29	99	77.34	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2366

1

T1

4

T2

28

T6

10

auto[1]

858

1

T4

34

T9

16

T19

18

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	368	1			T4	34		T10	22		T88	14
values[1]	402	1			T6	10		T93	30		T27	4
values[2]	302	1			T1	4		T41	8		T68	22
values[3]	452	1			T7	30		T9	16		T25	28
values[4]	286	1			T2	28		T43	18		T188	4
values[5]	448	1			T8	14		T72	14		T42	6
values[6]	388	1			T119	2		T227	4		T183	2
values[7]	578	1			T19	18		T26	26		T85	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	334	1			T4	34		T26	26		T68	22
values[1]	424	1			T72	14		T85	4		T119	2
values[2]	452	1			T7	30		T8	14		T41	8
values[3]	430	1			T1	4		T2	28		T25	28
values[4]	386	1			T6	10		T10	22		T19	18
values[5]	478	1			T9	16		T186	2		T121	4
values[6]	420	1			T71	24		T194	22		T290	14
values[7]	300	1			T187	4		T286	6		T51	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	29	99	77.34	29

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[3]]	[values[4]]	0	1	1
[auto[0]]	[values[4]]	[values[2]]	0	1	1
[auto[0]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[0]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[6]]	0	1	1
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[2]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[2]]	[values[6]]	0	1	1
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[4]]	[values[3]]	0	1	1
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[5]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[6]]	[values[4]]	0	1	1
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[3]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	38	1			T324	4		T201	4		T325	30
auto[0]	values[0]	values[1]	42	1			T256	6		T326	4		T283	2
auto[0]	values[0]	values[2]	14	1			T88	14		-	-		-	-
auto[0]	values[0]	values[3]	24	1			T91	22		T199	2		-	-
auto[0]	values[0]	values[4]	22	1			T10	22		-	-		-	-
auto[0]	values[0]	values[5]	4	1			T327	4		-	-		-	-
auto[0]	values[0]	values[6]	66	1			T214	4		T288	16		T328	10
auto[0]	values[0]	values[7]	4	1			T187	4		-	-		-	-
auto[0]	values[1]	values[0]	14	1			T329	10		T179	4		-	-
auto[0]	values[1]	values[1]	36	1			T263	20		T269	4		T296	12
auto[0]	values[1]	values[2]	26	1			T27	4		T171	4		T292	10
auto[0]	values[1]	values[3]	28	1			T280	28		-	-		-	-
auto[0]	values[1]	values[4]	90	1			T6	10		T93	30		T271	6
auto[0]	values[1]	values[5]	44	1			T191	6		T180	20		T195	18
auto[0]	values[1]	values[6]	40	1			T181	10		T268	8		T193	22
auto[0]	values[1]	values[7]	40	1			T286	6		T282	30		T86	4
auto[0]	values[2]	values[0]	16	1			T251	16		-	-		-	-
auto[0]	values[2]	values[1]	10	1			T330	10		-	-		-	-
auto[0]	values[2]	values[2]	50	1			T41	8		T224	4		T331	24
auto[0]	values[2]	values[3]	64	1			T1	4		T204	12		T332	24
auto[0]	values[2]	values[4]	4	1			T219	4		-	-		-	-
auto[0]	values[2]	values[5]	30	1			T192	4		T333	26		-	-
auto[0]	values[2]	values[6]	4	1			T298	4		-	-		-	-
auto[0]	values[2]	values[7]	28	1			T89	22		T247	6		-	-
auto[0]	values[3]	values[0]	4	1			T228	4		-	-		-	-
auto[0]	values[3]	values[1]	116	1			T44	28		T230	16		T334	30
auto[0]	values[3]	values[2]	74	1			T7	30		T56	22		T23	10
auto[0]	values[3]	values[3]	74	1			T25	28		T255	8		T115	14
auto[0]	values[3]	values[5]	2	1			T186	2		-	-		-	-
auto[0]	values[3]	values[6]	84	1			T71	24		T290	14		T234	26
auto[0]	values[3]	values[7]	38	1			T218	26		T335	8		T336	4
auto[0]	values[4]	values[0]	38	1			T69	12		T241	6		T337	20
auto[0]	values[4]	values[1]	4	1			T293	4		-	-		-	-
auto[0]	values[4]	values[3]	84	1			T2	28		T43	18		T207	28
auto[0]	values[4]	values[4]	14	1			T188	4		T302	10		-	-
auto[0]	values[4]	values[5]	56	1			T246	12		T338	4		T217	20
auto[0]	values[4]	values[6]	26	1			T197	8		T266	10		T210	8
auto[0]	values[5]	values[0]	2	1			T270	2		-	-		-	-
auto[0]	values[5]	values[1]	14	1			T72	14		-	-		-	-
auto[0]	values[5]	values[2]	162	1			T8	14		T54	30		T339	14
auto[0]	values[5]	values[3]	60	1			T42	6		T200	32		T226	22
auto[0]	values[5]	values[4]	18	1			T254	4		T340	2		T278	12
auto[0]	values[5]	values[5]	20	1			T275	20		-	-		-	-
auto[0]	values[5]	values[6]	12	1			T341	6		T342	6		-	-
auto[0]	values[5]	values[7]	28	1			T80	18		T343	8		T284	2
auto[0]	values[6]	values[0]	38	1			T262	4		T344	34		-	-
auto[0]	values[6]	values[1]	50	1			T119	2		T231	16		T345	12
auto[0]	values[6]	values[2]	36	1			T55	8		T235	8		T222	16
auto[0]	values[6]	values[3]	8	1			T28	6		T346	2		-	-
auto[0]	values[6]	values[4]	60	1			T183	2		T190	22		T237	2
auto[0]	values[6]	values[5]	78	1			T227	4		T87	4		T347	26
auto[0]	values[6]	values[6]	38	1			T194	22		T90	16		-	-
auto[0]	values[6]	values[7]	14	1			T229	6		T348	8		-	-
auto[0]	values[7]	values[0]	94	1			T26	26		T233	32		T349	18
auto[0]	values[7]	values[1]	44	1			T85	4		T196	10		T350	28
auto[0]	values[7]	values[2]	6	1			T221	6		-	-		-	-
auto[0]	values[7]	values[3]	50	1			T277	10		T208	6		T351	6
auto[0]	values[7]	values[4]	36	1			T184	14		T291	12		T264	10
auto[0]	values[7]	values[5]	50	1			T24	4		T215	36		T206	10
auto[0]	values[7]	values[6]	30	1			T287	30		-	-		-	-
auto[0]	values[7]	values[7]	66	1			T51	22		T92	12		T198	2
auto[1]	values[0]	values[0]	44	1			T4	34		T352	10		-	-
auto[1]	values[0]	values[1]	46	1			T279	32		T220	14		-	-
auto[1]	values[0]	values[2]	2	1			T203	2		-	-		-	-
auto[1]	values[0]	values[4]	20	1			T353	18		T244	2		-	-
auto[1]	values[0]	values[5]	34	1			T121	4		T242	12		T354	10
auto[1]	values[0]	values[7]	8	1			T79	8		-	-		-	-
auto[1]	values[1]	values[1]	4	1			T355	4		-	-		-	-
auto[1]	values[1]	values[2]	2	1			T75	2		-	-		-	-
auto[1]	values[1]	values[3]	4	1			T232	4		-	-		-	-
auto[1]	values[1]	values[4]	32	1			T73	32		-	-		-	-
auto[1]	values[1]	values[6]	30	1			T77	30		-	-		-	-
auto[1]	values[1]	values[7]	12	1			T205	12		-	-		-	-
auto[1]	values[2]	values[0]	22	1			T68	22		-	-		-	-
auto[1]	values[2]	values[1]	18	1			T189	18		-	-		-	-
auto[1]	values[2]	values[4]	12	1			T239	12		-	-		-	-
auto[1]	values[2]	values[5]	20	1			T78	20		-	-		-	-
auto[1]	values[2]	values[7]	24	1			T260	24		-	-		-	-
auto[1]	values[3]	values[1]	2	1			T356	2		-	-		-	-
auto[1]	values[3]	values[2]	10	1			T182	10		-	-		-	-
auto[1]	values[3]	values[5]	16	1			T9	16		-	-		-	-
auto[1]	values[3]	values[6]	32	1			T223	28		T261	4		-	-
auto[1]	values[4]	values[1]	14	1			T299	14		-	-		-	-
auto[1]	values[4]	values[2]	22	1			T300	22		-	-		-	-
auto[1]	values[4]	values[4]	28	1			T249	28		-	-		-	-
auto[1]	values[5]	values[0]	24	1			T74	24		-	-		-	-
auto[1]	values[5]	values[1]	12	1			T185	12		-	-		-	-
auto[1]	values[5]	values[2]	26	1			T238	8		T240	18		-	-
auto[1]	values[5]	values[3]	26	1			T76	26		-	-		-	-
auto[1]	values[5]	values[4]	32	1			T243	32		-	-		-	-
auto[1]	values[5]	values[7]	12	1			T253	12		-	-		-	-
auto[1]	values[6]	values[3]	8	1			T357	8		-	-		-	-
auto[1]	values[6]	values[5]	58	1			T281	30		T285	28		-	-
auto[1]	values[7]	values[1]	12	1			T358	12		-	-		-	-
auto[1]	values[7]	values[2]	22	1			T212	22		-	-		-	-
auto[1]	values[7]	values[4]	18	1			T19	18		-	-		-	-
auto[1]	values[7]	values[5]	66	1			T297	32		T213	34		-	-
auto[1]	values[7]	values[6]	58	1			T359	20		T252	22		T360	16
auto[1]	values[7]	values[7]	26	1			T225	26		-	-		-	-