Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	94	1			T88	10		T43	4		T56	6
auto[ReadAddrCrossIntoMailbox]	48	1			T6	2		T56	6		T263	4
auto[ReadAddrCrossOutOfMailbox]	46	1			T56	2		T263	2		T192	2
auto[ReadAddrCrossAllMailbox]	40	1			T56	2		T263	6		T216	2
auto[ReadAddrOutsideMailbox]	756	1			T2	14		T4	10		T6	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

492

1

T2

7

T4

5

T6

5

auto[1]

492

1

T2

7

T4

5

T6

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	172	1			T4	4		T6	8		T7	2
read_ops[0x0b]	114	1			T4	2		T8	2		T10	10
read_ops[0x3b]	158	1			T2	4		T4	2		T6	2
read_ops[0x6b]	190	1			T2	2		T19	2		T26	6
read_ops[0xbb]	168	1			T2	2		T4	2		T7	6
read_ops[0xeb]	182	1			T2	6		T41	2		T71	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T88	4		T263	1		T81	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T88	4		T263	1		T81	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T347	1		T81	1		T331	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T347	1		T81	1		T331	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T350	1		T345	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T350	1		T345	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T350	1		T283	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T350	1		T283	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	67	1			T4	2		T6	4		T7	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	67	1			T4	2		T6	4		T7	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T347	1		T259	2		T180	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T347	1		T259	2		T180	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T81	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T81	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T263	1		T171	1		T350	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T263	1		T171	1		T350	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T263	1		T345	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T263	1		T345	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	46	1			T4	1		T8	1		T10	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	46	1			T4	1		T8	1		T10	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T88	1		T347	1		T259	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T88	1		T347	1		T259	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	10	1			T6	1		T56	1		T263	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	10	1			T6	1		T56	1		T263	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T56	1		T216	1		T347	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T56	1		T216	1		T347	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T216	1		T347	1		T331	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T216	1		T347	1		T331	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	53	1			T2	2		T4	1		T25	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	53	1			T2	2		T4	1		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T56	2		T181	1		T343	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T56	2		T181	1		T343	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	6	1			T56	2		T192	1		T216	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	6	1			T56	2		T192	1		T216	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T347	2		T195	1		T245	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T347	2		T195	1		T245	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T56	1		T347	1		T350	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T56	1		T347	1		T350	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T2	1		T19	1		T26	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	72	1			T2	1		T19	1		T26	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T43	2		T181	1		T216	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T43	2		T181	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T195	1		T331	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T195	1		T331	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T171	1		T350	1		T331	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T171	1		T350	1		T331	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T263	1		T350	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T263	1		T350	1		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	66	1			T2	1		T4	1		T7	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	66	1			T2	1		T4	1		T7	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T56	1		T181	1		T269	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T56	1		T181	1		T269	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T245	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T245	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T192	1		T350	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T192	1		T350	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T263	1		T384	1		T195	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T263	1		T384	1		T195	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	74	1			T2	3		T41	1		T71	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	74	1			T2	3		T41	1		T71	1