Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	261921	1			T1	1		T2	1		T14	1
all_pins[1]	261921	1			T1	1		T2	1		T14	1
all_pins[2]	261921	1			T1	1		T2	1		T14	1
all_pins[3]	261921	1			T1	1		T2	1		T14	1
all_pins[4]	261921	1			T1	1		T2	1		T14	1
all_pins[5]	261921	1			T1	1		T2	1		T14	1
all_pins[6]	261921	1			T1	1		T2	1		T14	1
all_pins[7]	261921	1			T1	1		T2	1		T14	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2094453	1			T1	8		T2	8		T14	8
values[0x1]	915	1			T31	14		T33	52		T39	37
transitions[0x0=>0x1]	692	1			T31	9		T33	38		T39	26
transitions[0x1=>0x0]	706	1			T31	9		T33	39		T39	26

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	261808	1			T1	1		T2	1		T14	1
all_pins[0]	values[0x1]	113	1			T31	1		T33	7		T39	6
all_pins[0]	transitions[0x0=>0x1]	85	1			T31	1		T33	6		T39	3
all_pins[0]	transitions[0x1=>0x0]	84	1			T31	1		T33	3		T39	3
all_pins[1]	values[0x0]	261809	1			T1	1		T2	1		T14	1
all_pins[1]	values[0x1]	112	1			T31	1		T33	4		T39	6
all_pins[1]	transitions[0x0=>0x1]	73	1			T33	3		T39	4		T368	3
all_pins[1]	transitions[0x1=>0x0]	109	1			T31	2		T33	5		T39	6
all_pins[2]	values[0x0]	261773	1			T1	1		T2	1		T14	1
all_pins[2]	values[0x1]	148	1			T31	3		T33	6		T39	8
all_pins[2]	transitions[0x0=>0x1]	123	1			T31	3		T33	5		T39	6
all_pins[2]	transitions[0x1=>0x0]	60	1			T31	1		T33	5		T39	1
all_pins[3]	values[0x0]	261836	1			T1	1		T2	1		T14	1
all_pins[3]	values[0x1]	85	1			T31	1		T33	6		T39	3
all_pins[3]	transitions[0x0=>0x1]	63	1			T33	5		T39	1		T369	1
all_pins[3]	transitions[0x1=>0x0]	104	1			T31	1		T33	9		T39	4
all_pins[4]	values[0x0]	261795	1			T1	1		T2	1		T14	1
all_pins[4]	values[0x1]	126	1			T31	2		T33	10		T39	6
all_pins[4]	transitions[0x0=>0x1]	100	1			T31	1		T33	8		T39	5
all_pins[4]	transitions[0x1=>0x0]	70	1			T31	1		T33	2		T39	1
all_pins[5]	values[0x0]	261825	1			T1	1		T2	1		T14	1
all_pins[5]	values[0x1]	96	1			T31	2		T33	4		T39	2
all_pins[5]	transitions[0x0=>0x1]	79	1			T31	2		T33	4		T39	2
all_pins[5]	transitions[0x1=>0x0]	107	1			T31	1		T33	5		T39	4
all_pins[6]	values[0x0]	261797	1			T1	1		T2	1		T14	1
all_pins[6]	values[0x1]	124	1			T31	1		T33	5		T39	4
all_pins[6]	transitions[0x0=>0x1]	90	1			T33	1		T39	4		T368	3
all_pins[6]	transitions[0x1=>0x0]	77	1			T31	2		T33	6		T39	2
all_pins[7]	values[0x0]	261810	1			T1	1		T2	1		T14	1
all_pins[7]	values[0x1]	111	1			T31	3		T33	10		T39	2
all_pins[7]	transitions[0x0=>0x1]	79	1			T31	2		T33	6		T39	1
all_pins[7]	transitions[0x1=>0x0]	95	1			T33	4		T39	5		T368	2