Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.01	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	54	74	57.81

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	54	74	57.81	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	432	1			T72	14		T182	10		T119	2
values[1]	550	1			T10	22		T19	18		T25	28
values[2]	302	1			T1	4		T8	14		T41	8
values[3]	362	1			T4	34		T183	2		T28	6
values[4]	324	1			T2	28		T7	30		T9	16
values[5]	316	1			T26	26		T184	14		T185	12
values[6]	460	1			T186	2		T88	14		T27	4
values[7]	478	1			T6	10		T93	30		T68	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	332	1			T1	4		T2	28		T19	18
values[1]	458	1			T27	4		T68	22		T187	4
values[2]	406	1			T4	34		T8	14		T119	2
values[3]	240	1			T9	16		T23	10		T87	4
values[4]	470	1			T93	30		T186	2		T42	6
values[5]	392	1			T10	22		T41	8		T72	14
values[6]	506	1			T71	24		T44	28		T188	4
values[7]	420	1			T6	10		T7	30		T25	28

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3186

1

T1

4

T2

28

T4

30

auto[1]

38

1

T4

4

T19

2

T68

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	54	74	57.81	54

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[0]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[1]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[2]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	7
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	64	1			T189	18		T190	22		T191	6
auto[0]	values[0]	values[1]	74	1			T187	4		T192	4		T193	22
auto[0]	values[0]	values[2]	56	1			T119	2		T194	22		T195	18
auto[0]	values[0]	values[3]	72	1			T76	24		T91	22		T196	10
auto[0]	values[0]	values[4]	12	1			T197	8		T198	2		T199	2
auto[0]	values[0]	values[5]	74	1			T72	14		T182	10		T200	32
auto[0]	values[0]	values[6]	64	1			T80	18		T201	4		T202	18
auto[0]	values[0]	values[7]	14	1			T203	2		T204	12		-	-
auto[0]	values[1]	values[0]	44	1			T19	16		T205	12		T206	10
auto[0]	values[1]	values[1]	78	1			T207	28		T208	6		T209	24
auto[0]	values[1]	values[2]	16	1			T210	8		T211	8		-	-
auto[0]	values[1]	values[3]	22	1			T212	22		-	-		-	-
auto[0]	values[1]	values[4]	94	1			T213	34		T89	22		T77	26
auto[0]	values[1]	values[5]	66	1			T10	22		T214	4		T215	36
auto[0]	values[1]	values[6]	148	1			T44	28		T74	22		T216	16
auto[0]	values[1]	values[7]	72	1			T25	28		T85	4		T217	20
auto[0]	values[2]	values[0]	4	1			T1	4		-	-		-	-
auto[0]	values[2]	values[1]	40	1			T218	26		T81	14		-	-
auto[0]	values[2]	values[2]	32	1			T8	14		T219	4		T220	14
auto[0]	values[2]	values[3]	6	1			T221	6		-	-		-	-
auto[0]	values[2]	values[4]	120	1			T42	6		T222	16		T223	28
auto[0]	values[2]	values[5]	16	1			T41	8		T224	4		T86	4
auto[0]	values[2]	values[6]	48	1			T225	26		T226	22		-	-
auto[0]	values[2]	values[7]	34	1			T227	4		T228	4		T229	6
auto[0]	values[3]	values[0]	16	1			T230	16		-	-		-	-
auto[0]	values[3]	values[1]	70	1			T90	16		T231	16		T232	4
auto[0]	values[3]	values[2]	88	1			T4	30		T233	32		T234	26
auto[0]	values[3]	values[3]	10	1			T23	10		-	-		-	-
auto[0]	values[3]	values[4]	38	1			T28	6		T235	8		T236	24
auto[0]	values[3]	values[5]	34	1			T237	2		T238	8		T239	12
auto[0]	values[3]	values[6]	42	1			T188	4		T240	18		T241	6
auto[0]	values[3]	values[7]	58	1			T183	2		T242	12		T243	32
auto[0]	values[4]	values[0]	28	1			T2	28		-	-		-	-
auto[0]	values[4]	values[1]	60	1			T69	12		T244	2		T245	16
auto[0]	values[4]	values[2]	52	1			T73	24		T246	12		T171	4
auto[0]	values[4]	values[3]	34	1			T9	16		T87	4		T247	6
auto[0]	values[4]	values[4]	48	1			T248	16		T249	28		T250	4
auto[0]	values[4]	values[5]	20	1			T121	4		T251	16		-	-
auto[0]	values[4]	values[6]	22	1			T252	22		-	-		-	-
auto[0]	values[4]	values[7]	52	1			T7	30		T253	12		T254	4
auto[0]	values[5]	values[0]	104	1			T26	26		T185	12		T255	8
auto[0]	values[5]	values[1]	30	1			T92	12		T256	6		T257	12
auto[0]	values[5]	values[2]	24	1			T258	24		-	-		-	-
auto[0]	values[5]	values[3]	44	1			T259	10		T260	24		T261	4
auto[0]	values[5]	values[4]	24	1			T262	4		T263	20		-	-
auto[0]	values[5]	values[5]	70	1			T184	14		T264	10		T265	22
auto[0]	values[5]	values[6]	12	1			T266	10		T267	2		-	-
auto[0]	values[5]	values[7]	8	1			T268	8		-	-		-	-
auto[0]	values[6]	values[0]	38	1			T56	22		T269	4		T270	2
auto[0]	values[6]	values[1]	20	1			T27	4		T271	6		T272	6
auto[0]	values[6]	values[2]	60	1			T55	8		T273	16		T274	12
auto[0]	values[6]	values[3]	4	1			T24	4		-	-		-	-
auto[0]	values[6]	values[4]	66	1			T186	2		T275	20		T276	22
auto[0]	values[6]	values[5]	42	1			T277	10		T180	20		T278	12
auto[0]	values[6]	values[6]	106	1			T279	32		T280	28		T281	30
auto[0]	values[6]	values[7]	118	1			T88	14		T70	12		T282	30
auto[0]	values[7]	values[0]	32	1			T283	2		T284	2		T285	28
auto[0]	values[7]	values[1]	82	1			T68	18		T286	6		T287	30
auto[0]	values[7]	values[2]	66	1			T181	10		T288	16		T289	40
auto[0]	values[7]	values[3]	46	1			T290	14		T291	12		T292	10
auto[0]	values[7]	values[4]	62	1			T93	30		T51	22		T293	4
auto[0]	values[7]	values[5]	68	1			T43	18		T54	30		T294	10
auto[0]	values[7]	values[6]	60	1			T71	24		T295	20		T296	12
auto[0]	values[7]	values[7]	58	1			T6	10		T297	32		T298	4
auto[1]	values[0]	values[3]	2	1			T76	2		-	-		-	-
auto[1]	values[1]	values[0]	2	1			T19	2		-	-		-	-
auto[1]	values[1]	values[4]	4	1			T77	4		-	-		-	-
auto[1]	values[1]	values[6]	4	1			T74	2		T78	2		-	-
auto[1]	values[2]	values[4]	2	1			T79	2		-	-		-	-
auto[1]	values[3]	values[2]	4	1			T4	4		-	-		-	-
auto[1]	values[3]	values[5]	2	1			T299	2		-	-		-	-
auto[1]	values[4]	values[2]	8	1			T73	8		-	-		-	-
auto[1]	values[6]	values[7]	6	1			T75	2		T300	4		-	-
auto[1]	values[7]	values[1]	4	1			T68	4		-	-		-	-