Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1439

1

T11

22

T12

2

T21

11

auto[1]

1393

1

T11

28

T12

4

T21

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694

1

T22

12

T58

2

T61

8

auto[1]

2138

1

T11

50

T12

6

T21

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2555

1

T11

50

T12

6

T21

14

auto[1]

277

1

T22

4

T61

7

T63

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	554	1			T11	7		T12	1		T21	1
valid[1]	610	1			T11	11		T12	1		T21	7
valid[2]	568	1			T11	9		T12	1		T21	4
valid[3]	560	1			T11	12		T12	2		T21	2
valid[4]	540	1			T11	11		T12	1		T22	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	47	1			T22	2		T58	1		T100	3
auto[0]	auto[0]	valid[0]	auto[1]	214	1			T11	3		T12	1		T21	1
auto[0]	auto[0]	valid[1]	auto[0]	50	1			T22	1		T100	1		T401	4
auto[0]	auto[0]	valid[1]	auto[1]	219	1			T11	6		T21	6		T60	2
auto[0]	auto[0]	valid[2]	auto[0]	37	1			T22	1		T58	1		T100	1
auto[0]	auto[0]	valid[2]	auto[1]	217	1			T11	2		T21	2		T60	1
auto[0]	auto[0]	valid[3]	auto[0]	44	1			T22	1		T63	1		T100	2
auto[0]	auto[0]	valid[3]	auto[1]	210	1			T11	7		T12	1		T21	2
auto[0]	auto[0]	valid[4]	auto[0]	50	1			T61	1		T63	1		T100	2
auto[0]	auto[0]	valid[4]	auto[1]	221	1			T11	4		T60	3		T104	1
auto[0]	auto[1]	valid[0]	auto[0]	42	1			T102	2		T401	5		T398	1
auto[0]	auto[1]	valid[0]	auto[1]	205	1			T11	4		T60	4		T105	2
auto[0]	auto[1]	valid[1]	auto[0]	41	1			T100	2		T102	2		T401	1
auto[0]	auto[1]	valid[1]	auto[1]	223	1			T11	5		T12	1		T21	1
auto[0]	auto[1]	valid[2]	auto[0]	31	1			T398	1		T402	1		T387	3
auto[0]	auto[1]	valid[2]	auto[1]	227	1			T11	7		T12	1		T21	2
auto[0]	auto[1]	valid[3]	auto[0]	34	1			T102	3		T103	1		T398	2
auto[0]	auto[1]	valid[3]	auto[1]	227	1			T11	5		T12	1		T60	1
auto[0]	auto[1]	valid[4]	auto[0]	41	1			T22	3		T102	4		T401	2
auto[0]	auto[1]	valid[4]	auto[1]	175	1			T11	7		T12	1		T60	2
auto[1]	auto[0]	valid[0]	auto[0]	22	1			T102	1		T401	1		T385	1
auto[1]	auto[0]	valid[1]	auto[0]	42	1			T61	1		T63	1		T100	1
auto[1]	auto[0]	valid[2]	auto[0]	22	1			T401	2		T402	2		T177	1
auto[1]	auto[0]	valid[3]	auto[0]	20	1			T22	1		T61	1		T401	1
auto[1]	auto[0]	valid[4]	auto[0]	24	1			T100	2		T401	1		T101	1
auto[1]	auto[1]	valid[0]	auto[0]	24	1			T61	1		T102	1		T387	3
auto[1]	auto[1]	valid[1]	auto[0]	35	1			T22	1		T61	1		T100	1
auto[1]	auto[1]	valid[2]	auto[0]	34	1			T22	1		T102	3		T401	2
auto[1]	auto[1]	valid[3]	auto[0]	25	1			T22	1		T61	2		T402	1
auto[1]	auto[1]	valid[4]	auto[0]	29	1			T61	1		T102	1		T401	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal