Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17145

1

T13

19

T17

12

T18

4

auto[1]

19955

1

T11

637

T12

6

T21

147

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30875

1

T11

637

T12

6

T13

11

auto[1]

6225

1

T13

8

T17

8

T18

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19334	1			T11	312		T12	6		T13	10
others[1]	3002	1			T11	57		T13	2		T17	1
others[2]	3106	1			T11	49		T13	2		T17	1
others[3]	3513	1			T11	57		T13	2		T17	2
interest[1]	2065	1			T11	36		T21	4		T22	12
interest[4]	12837	1			T11	203		T12	6		T13	9
interest[64]	6080	1			T11	126		T13	3		T17	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5535	1			T13	5		T17	2		T22	69
auto[0]	auto[0]	others[1]	955	1			T13	2		T17	1		T22	12
auto[0]	auto[0]	others[2]	933	1			T18	1		T22	8		T58	1
auto[0]	auto[0]	others[3]	1013	1			T13	1		T22	12		T58	2
auto[0]	auto[0]	interest[1]	640	1			T22	7		T61	1		T63	1
auto[0]	auto[0]	interest[4]	3622	1			T13	5		T17	1		T22	43
auto[0]	auto[0]	interest[64]	1844	1			T13	3		T17	1		T22	17
auto[0]	auto[1]	others[0]	10568	1			T11	312		T12	6		T21	73
auto[0]	auto[1]	others[1]	1557	1			T11	57		T21	7		T22	3
auto[0]	auto[1]	others[2]	1672	1			T11	49		T21	16		T22	4
auto[0]	auto[1]	others[3]	1865	1			T11	57		T21	21		T22	1
auto[0]	auto[1]	interest[1]	1072	1			T11	36		T21	4		T104	12
auto[0]	auto[1]	interest[4]	7122	1			T11	203		T12	6		T21	50
auto[0]	auto[1]	interest[64]	3221	1			T11	126		T21	26		T22	1
auto[1]	auto[0]	others[0]	3231	1			T13	5		T17	5		T18	3
auto[1]	auto[0]	others[1]	490	1			T22	5		T58	1		T61	1
auto[1]	auto[0]	others[2]	501	1			T13	2		T17	1		T22	10
auto[1]	auto[0]	others[3]	635	1			T13	1		T17	2		T22	7
auto[1]	auto[0]	interest[1]	353	1			T22	5		T61	3		T62	1
auto[1]	auto[0]	interest[4]	2093	1			T13	4		T17	3		T18	2
auto[1]	auto[0]	interest[64]	1015	1			T22	10		T58	3		T61	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal