Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	499	1			T31	10		T33	28		T39	14
all_values[1]	499	1			T31	10		T33	28		T39	14
all_values[2]	499	1			T31	10		T33	28		T39	14
all_values[3]	499	1			T31	10		T33	28		T39	14
all_values[4]	499	1			T31	10		T33	28		T39	14
all_values[5]	499	1			T31	10		T33	28		T39	14
all_values[6]	499	1			T31	10		T33	28		T39	14
all_values[7]	499	1			T31	10		T33	28		T39	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2144

1

T31

41

T33

131

T39

57

auto[1]

1848

1

T31

39

T33

93

T39

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1602

1

T31

37

T33

83

T39

42

auto[1]

2390

1

T31

43

T33

141

T39

70

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2302

1

T31

46

T33

124

T39

62

auto[1]

1690

1

T31

34

T33

100

T39

50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	90	1			T31	4		T33	5		T39	3
all_values[0]	auto[0]	auto[0]	auto[1]	48	1			T33	6		T368	2		T369	2
all_values[0]	auto[0]	auto[1]	auto[0]	95	1			T33	1		T368	5		T370	3
all_values[0]	auto[0]	auto[1]	auto[1]	54	1			T31	1		T33	2		T39	3
all_values[0]	auto[1]	auto[0]	auto[1]	117	1			T31	4		T33	6		T39	5
all_values[0]	auto[1]	auto[1]	auto[1]	95	1			T31	1		T33	8		T39	3
all_values[1]	auto[0]	auto[0]	auto[0]	112	1			T31	3		T33	10		T39	2
all_values[1]	auto[0]	auto[0]	auto[1]	49	1			T31	1		T33	2		T370	1
all_values[1]	auto[0]	auto[1]	auto[0]	86	1			T31	2		T33	3		T39	2
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T31	1		T33	2		T39	2
all_values[1]	auto[1]	auto[0]	auto[1]	121	1			T31	2		T33	8		T39	4
all_values[1]	auto[1]	auto[1]	auto[1]	87	1			T31	1		T33	3		T39	4
all_values[2]	auto[0]	auto[0]	auto[0]	90	1			T31	1		T33	6		T368	2
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T33	2		T39	1		T368	3
all_values[2]	auto[0]	auto[1]	auto[0]	67	1			T31	3		T33	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[1]	62	1			T33	3		T39	3		T369	1
all_values[2]	auto[1]	auto[0]	auto[1]	124	1			T31	2		T33	10		T39	4
all_values[2]	auto[1]	auto[1]	auto[1]	106	1			T31	4		T33	6		T39	5
all_values[3]	auto[0]	auto[0]	auto[0]	101	1			T31	3		T33	7		T39	5
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T33	2		T39	1		T368	2
all_values[3]	auto[0]	auto[1]	auto[0]	95	1			T31	3		T33	5		T39	3
all_values[3]	auto[0]	auto[1]	auto[1]	35	1			T31	1		T33	4		T39	1
all_values[3]	auto[1]	auto[0]	auto[1]	125	1			T31	1		T33	8		T39	1
all_values[3]	auto[1]	auto[1]	auto[1]	86	1			T31	2		T33	2		T39	3
all_values[4]	auto[0]	auto[0]	auto[0]	96	1			T33	5		T39	3		T368	3
all_values[4]	auto[0]	auto[0]	auto[1]	51	1			T33	4		T39	1		T368	1
all_values[4]	auto[0]	auto[1]	auto[0]	89	1			T31	3		T33	1		T39	1
all_values[4]	auto[0]	auto[1]	auto[1]	53	1			T31	1		T33	5		T39	4
all_values[4]	auto[1]	auto[0]	auto[1]	113	1			T31	2		T33	9		T39	2
all_values[4]	auto[1]	auto[1]	auto[1]	97	1			T31	4		T33	4		T39	3
all_values[5]	auto[0]	auto[0]	auto[0]	144	1			T31	4		T33	5		T39	6
all_values[5]	auto[0]	auto[1]	auto[0]	145	1			T31	2		T33	14		T39	1
all_values[5]	auto[1]	auto[0]	auto[1]	119	1			T31	3		T33	4		T39	5
all_values[5]	auto[1]	auto[1]	auto[1]	91	1			T31	1		T33	5		T39	2
all_values[6]	auto[0]	auto[0]	auto[0]	108	1			T31	4		T33	6		T39	3
all_values[6]	auto[0]	auto[0]	auto[1]	49	1			T33	1		T368	1		T369	3
all_values[6]	auto[0]	auto[1]	auto[0]	90	1			T31	2		T33	7		T39	3
all_values[6]	auto[0]	auto[1]	auto[1]	49	1			T31	1		T33	1		T39	3
all_values[6]	auto[1]	auto[0]	auto[1]	110	1			T31	2		T33	10		T39	3
all_values[6]	auto[1]	auto[1]	auto[1]	93	1			T31	1		T33	3		T39	2
all_values[7]	auto[0]	auto[0]	auto[0]	100	1			T31	1		T33	4		T39	6
all_values[7]	auto[0]	auto[0]	auto[1]	56	1			T31	1		T33	3		T39	1
all_values[7]	auto[0]	auto[1]	auto[0]	94	1			T31	2		T33	3		T39	3
all_values[7]	auto[0]	auto[1]	auto[1]	43	1			T31	2		T33	4		T368	2
all_values[7]	auto[1]	auto[0]	auto[1]	114	1			T31	3		T33	8		T39	1
all_values[7]	auto[1]	auto[1]	auto[1]	92	1			T31	1		T33	6		T39	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal