Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	306126	1			T1	1528		T2	1		T3	5640
all_values[1]	306126	1			T1	1528		T2	1		T3	5640
all_values[2]	306126	1			T1	1528		T2	1		T3	5640
all_values[3]	306126	1			T1	1528		T2	1		T3	5640
all_values[4]	306126	1			T1	1528		T2	1		T3	5640
all_values[5]	306126	1			T1	1528		T2	1		T3	5640
all_values[6]	306126	1			T1	1528		T2	1		T3	5640
all_values[7]	306126	1			T1	1528		T2	1		T3	5640

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2446699

1

T1

12224

T2

8

T3

45120

auto[1]

2309

1

T19

55

T35

64

T36

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2446913

1

T1

12214

T2

8

T3

45120

auto[1]

2095

1

T1

10

T13

11

T19

31

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	305737	1			T1	1528		T2	1		T3	5640
all_values[0]	auto[0]	auto[1]	118	1			T19	3		T35	2		T37	2
all_values[0]	auto[1]	auto[0]	146	1			T19	6		T35	6		T36	5
all_values[0]	auto[1]	auto[1]	125	1			T19	2		T35	5		T36	1
all_values[1]	auto[0]	auto[0]	305726	1			T1	1528		T2	1		T3	5640
all_values[1]	auto[0]	auto[1]	100	1			T19	3		T35	2		T37	2
all_values[1]	auto[1]	auto[0]	191	1			T19	1		T35	5		T36	1
all_values[1]	auto[1]	auto[1]	109	1			T19	1		T35	3		T37	4
all_values[2]	auto[0]	auto[0]	305714	1			T1	1528		T2	1		T3	5640
all_values[2]	auto[0]	auto[1]	122	1			T19	1		T36	1		T37	2
all_values[2]	auto[1]	auto[0]	187	1			T19	7		T35	3		T36	1
all_values[2]	auto[1]	auto[1]	103	1			T19	3		T35	1		T37	1
all_values[3]	auto[0]	auto[0]	305691	1			T1	1528		T2	1		T3	5640
all_values[3]	auto[0]	auto[1]	120	1			T35	7		T36	1		T359	4
all_values[3]	auto[1]	auto[0]	185	1			T19	5		T35	2		T36	5
all_values[3]	auto[1]	auto[1]	130	1			T19	5		T35	3		T359	3
all_values[4]	auto[0]	auto[0]	305697	1			T1	1528		T2	1		T3	5640
all_values[4]	auto[0]	auto[1]	142	1			T19	4		T35	6		T36	1
all_values[4]	auto[1]	auto[0]	161	1			T19	2		T35	2		T37	4
all_values[4]	auto[1]	auto[1]	126	1			T35	2		T36	1		T37	5
all_values[5]	auto[0]	auto[0]	305475	1			T1	1518		T2	1		T3	5640
all_values[5]	auto[0]	auto[1]	363	1			T1	10		T13	11		T19	1
all_values[5]	auto[1]	auto[0]	175	1			T19	9		T35	6		T37	7
all_values[5]	auto[1]	auto[1]	113	1			T35	5		T36	2		T37	2
all_values[6]	auto[0]	auto[0]	305743	1			T1	1528		T2	1		T3	5640
all_values[6]	auto[0]	auto[1]	122	1			T19	2		T35	3		T37	1
all_values[6]	auto[1]	auto[0]	167	1			T19	3		T35	5		T36	5
all_values[6]	auto[1]	auto[1]	94	1			T19	1		T35	4		T37	1
all_values[7]	auto[0]	auto[0]	305718	1			T1	1528		T2	1		T3	5640
all_values[7]	auto[0]	auto[1]	111	1			T19	2		T36	3		T37	3
all_values[7]	auto[1]	auto[0]	200	1			T19	7		T35	6		T37	3
all_values[7]	auto[1]	auto[1]	97	1			T19	3		T35	6		T37	1