Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	27	57	67.86

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	25	23	47.92	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1103	1			T2	8		T4	2		T6	8
auto[SpiFlashAddrCfg]	901	1			T2	4		T4	4		T6	3
auto[SpiFlashAddr3b]	1110	1			T5	4		T6	7		T7	2
auto[SpiFlashAddr4b]	914	1			T2	10		T4	2		T5	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3060

1

T2

22

T4

8

T5

8

auto[1]

968

1

T6

8

T62

22

T64

28

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2050

1

T2

6

T5

8

T6

15

auto[1]

1978

1

T2

16

T4

8

T6

5

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1601	1			T2	14		T4	6		T6	12
values[1]	77	1			T2	2		T124	1		T69	4
values[2]	196	1			T86	3		T63	4		T125	4
values[3]	229	1			T5	4		T7	2		T10	6
values[4]	170	1			T6	1		T62	4		T94	6
values[5]	205	1			T6	1		T7	4		T61	2
values[6]	147	1			T6	1		T11	2		T12	8
values[7]	246	1			T2	2		T8	2		T78	2
values[8]	1157	1			T2	4		T4	2		T5	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3528

1

T2

22

T4

8

T7

10

auto[1]

500

1

T5

8

T6

20

T9

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3894

1

T2

22

T4

8

T5

8

write

134

1

T61

8

T62

6

T63

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1870

1

T2

6

T4

4

T5

4

valids[0x1]

2158

1

T2

16

T4

4

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	192	1			T2	2		T4	2		T6	1
internal_process_ops[0x5a]	233	1			T6	1		T7	2		T12	2
internal_process_ops[0x05]	209	1			T2	4		T6	2		T10	2
internal_process_ops[0x35]	156	1			T6	1		T63	4		T186	4
internal_process_ops[0x15]	212	1			T2	2		T6	2		T7	2
internal_process_ops[0x03]	297	1			T2	2		T5	4		T9	7
internal_process_ops[0x0b]	238	1			T4	2		T11	4		T12	2
internal_process_ops[0x3b]	288	1			T6	1		T7	4		T8	2
internal_process_ops[0x6b]	255	1			T5	4		T12	4		T45	4
internal_process_ops[0xbb]	278	1			T12	6		T63	2		T184	4
internal_process_ops[0xeb]	233	1			T6	1		T86	4		T61	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3982

1

T2

22

T4

8

T5

8

auto[1]

46

1

T62

6

T64

4

T66

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4028

1

T2

22

T4

8

T5

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	25	23	47.92	25
Automatically Generated Cross Bins	48	25	23	47.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

819

1

T2

8

T4

2

T7

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

247

1

T62

6

T64

8

T65

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

472

1

T2

4

T4

4

T7

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

226

1

T66

10

T186

2

T69

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

726

1

T7

2

T8

2

T10

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

209

1

T62

6

T64

4

T65

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

463

1

T2

10

T4

2

T10

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

232

1

T62

4

T64

12

T65

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12

1

T61

2

T229

2

T220

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

14

1

T62

4

T73

2

T74

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

28

1

T61

6

T96

4

T261

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

6

1

T66

4

T72

2

-

-

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

36

1

T63

6

T30

2

T208

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

10

1

T62

2

T69

4

T72

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

12

1

T211

4

T323

2

T297

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

16

1

T64

4

T70

2

T71

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7

1

T6

4

T339

3

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4

1

T6

4

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

169

1

T6

3

T86

3

T124

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T5

4

T6

5

T9

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2

1

T6

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

189

1

T5

4

T124

5

T111

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2

1

T6

2

-

-

-

-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	291	1			T4	2		T10	2		T27	4
auto[0]	values[0]	valids[0x1]	1232	1			T2	14		T4	4		T7	4
auto[0]	values[1]	valids[0x1]	76	1			T2	2		T69	4		T216	2
auto[0]	values[2]	valids[0x0]	101	1			T63	2		T125	4		T239	2
auto[0]	values[2]	valids[0x1]	68	1			T63	2		T64	6		T96	6
auto[0]	values[3]	valids[0x0]	166	1			T10	6		T12	6		T45	12
auto[0]	values[3]	valids[0x1]	20	1			T7	2		T247	2		T300	4
auto[0]	values[4]	valids[0x0]	73	1			T62	4		T64	2		T173	6
auto[0]	values[4]	valids[0x1]	54	1			T94	6		T207	2		T178	4
auto[0]	values[5]	valids[0x0]	90	1			T7	4		T61	2		T176	2
auto[0]	values[5]	valids[0x1]	70	1			T94	8		T64	4		T261	2
auto[0]	values[6]	valids[0x0]	58	1			T11	2		T12	4		T94	2
auto[0]	values[6]	valids[0x1]	50	1			T12	4		T261	2		T173	2
auto[0]	values[7]	valids[0x0]	125	1			T2	2		T8	2		T78	2
auto[0]	values[7]	valids[0x1]	74	1			T83	2		T94	4		T176	2
auto[0]	values[8]	valids[0x0]	633	1			T2	4		T4	2		T10	8
auto[0]	values[8]	valids[0x1]	347	1			T11	4		T12	4		T87	4
auto[1]	values[0]	valids[0x0]	5	1			T6	5		-	-		-	-
auto[1]	values[0]	valids[0x1]	73	1			T6	7		T111	5		T340	4
auto[1]	values[1]	valids[0x1]	1	1			T124	1		-	-		-	-
auto[1]	values[2]	valids[0x0]	16	1			T86	3		T341	6		T342	7
auto[1]	values[2]	valids[0x1]	11	1			T343	11		-	-		-	-
auto[1]	values[3]	valids[0x0]	41	1			T5	4		T344	3		T345	6
auto[1]	values[3]	valids[0x1]	2	1			T346	2		-	-		-	-
auto[1]	values[4]	valids[0x0]	26	1			T6	1		T340	4		T347	5
auto[1]	values[4]	valids[0x1]	17	1			T348	3		T349	7		T350	3
auto[1]	values[5]	valids[0x0]	42	1			T6	1		T124	5		T351	8
auto[1]	values[5]	valids[0x1]	3	1			T348	3		-	-		-	-
auto[1]	values[6]	valids[0x0]	24	1			T124	5		T344	8		T347	2
auto[1]	values[6]	valids[0x1]	15	1			T6	1		T346	7		T352	7
auto[1]	values[7]	valids[0x0]	43	1			T111	5		T344	3		T353	6
auto[1]	values[7]	valids[0x1]	4	1			T354	4		-	-		-	-
auto[1]	values[8]	valids[0x0]	136	1			T6	4		T86	4		T111	6
auto[1]	values[8]	valids[0x1]	41	1			T5	4		T6	1		T9	7