Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
36.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	2	14	87.50
Crosses	72	54	18	25.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	1	1	50.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	48	16	25.00	100	1	1	0
cr_busyXwelXcsb	8	6	2	25.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_busy_bit

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1641561

1

T2

1

T4

1

T5

5034

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1545558

1

T2

1

T4

1

T5

5034

auto[1]

96003

1

T6

2317

T10

5796

T12

568

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	375014	1			T2	1		T4	1		T5	947
auto[524288:1048575]	194782	1			T5	1427		T7	512		T9	541
auto[1048576:1572863]	170025	1			T5	133		T9	7095		T12	1
auto[1572864:2097151]	148607	1			T5	541		T7	3		T8	11
auto[2097152:2621439]	200833	1			T5	387		T7	195		T9	2289
auto[2621440:3145727]	165149	1			T5	374		T6	1540		T7	145
auto[3145728:3670015]	204842	1			T6	782		T7	556		T12	31
auto[3670016:4194303]	182309	1			T5	1225		T7	420		T8	5

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109968

1

T2

1

T4

1

T5

228

auto[1]

1531593

1

T5

4806

T7

3096

T8

352

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_wel_bit

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1641561

1

T2

1

T4

1

T5

5034

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	48	16	25.00	48

Automatically Generated Cross Bins for cr_all_except_csb

Element holes

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	*	--	--	16
[auto[1]]	*	*	*	--	--	32

Covered bins

cp_busy_bit

cp_wel_bit

cp_other_status

cp_is_host_read

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0:524287]

auto[0]

301323

1

T2

1

T4

1

T5

947

auto[0]

auto[0]

auto[0:524287]

auto[1]

73691

1

T10

5796

T92

8

T30

256

auto[0]

auto[0]

auto[524288:1048575]

auto[0]

191501

1

T5

1427

T7

512

T9

541

auto[0]

auto[0]

auto[524288:1048575]

auto[1]

3281

1

T12

288

T177

5

T178

29

auto[0]

auto[0]

auto[1048576:1572863]

auto[0]

166954

1

T5

133

T9

7095

T12

1

auto[0]

auto[0]

auto[1048576:1572863]

auto[1]

3071

1

T179

12

T180

29

T181

16

auto[0]

auto[0]

auto[1572864:2097151]

auto[0]

145150

1

T5

541

T7

3

T8

11

auto[0]

auto[0]

auto[1572864:2097151]

auto[1]

3457

1

T179

911

T177

2

T178

265

auto[0]

auto[0]

auto[2097152:2621439]

auto[0]

199633

1

T5

387

T7

195

T9

2289

auto[0]

auto[0]

auto[2097152:2621439]

auto[1]

1200

1

T179

120

T182

1

T183

2

auto[0]

auto[0]

auto[2621440:3145727]

auto[0]

160027

1

T5

374

T6

4

T7

145

auto[0]

auto[0]

auto[2621440:3145727]

auto[1]

5122

1

T6

1536

T177

1

T178

34

auto[0]

auto[0]

auto[3145728:3670015]

auto[0]

200114

1

T6

1

T7

556

T12

31

auto[0]

auto[0]

auto[3145728:3670015]

auto[1]

4728

1

T6

781

T179

512

T177

2

auto[0]

auto[0]

auto[3670016:4194303]

auto[0]

180856

1

T5

1225

T7

420

T8

5

auto[0]

auto[0]

auto[3670016:4194303]

auto[1]

1453

1

T12

280

T179

1

T177

7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	6	2	25.00	6

Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	*	*	--	--	4

Covered bins

cp_busy_bit

cp_wel_bit

cp_sw_read_while_csb_active

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

109968

1

T2

1

T4

1

T5

228

auto[0]

auto[0]

auto[1]

1531593

1

T5

4806

T7

3096

T8

352