Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	34	94	73.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	34	94	73.44	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2568

1

T2

22

T4

8

T7

10

auto[1]

960

1

T62

22

T64

28

T65

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	456	1			T12	30		T95	4		T261	12
values[1]	498	1			T27	4		T79	6		T187	20
values[2]	386	1			T7	10		T184	8		T186	20
values[3]	386	1			T2	22		T8	2		T87	8
values[4]	484	1			T10	20		T83	6		T29	2
values[5]	458	1			T61	22		T63	28		T239	2
values[6]	398	1			T4	8		T78	4		T94	28
values[7]	462	1			T11	8		T62	22		T125	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	326	1			T2	22		T125	6		T64	28
values[1]	536	1			T27	4		T45	26		T30	20
values[2]	300	1			T66	32		T186	20		T69	16
values[3]	318	1			T4	8		T95	4		T185	2
values[4]	496	1			T12	30		T78	4		T79	6
values[5]	464	1			T7	10		T8	2		T92	2
values[6]	444	1			T87	8		T65	10		T96	36
values[7]	644	1			T10	20		T11	8		T61	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	34	94	73.44	34

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[2]]	0	1	1
[auto[0]]	[values[4]]	[values[1]]	0	1	1
[auto[0]]	[values[6]]	[values[6]]	0	1	1
[auto[0]]	[values[7]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[0]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2]]	0	1	1
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[2]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[2]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[6]]	[values[6]]	0	1	1
[auto[1]]	[values[7]]	[values[1]]	0	1	1
[auto[1]]	[values[7]]	[values[3]]	0	1	1
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	40	1			T233	34		T256	6		-	-
auto[0]	values[0]	values[1]	56	1			T199	22		T236	14		T293	20
auto[0]	values[0]	values[2]	44	1			T180	14		T288	30		-	-
auto[0]	values[0]	values[3]	54	1			T95	4		T182	24		T198	2
auto[0]	values[0]	values[4]	74	1			T12	30		T225	16		T223	28
auto[0]	values[0]	values[5]	76	1			T261	12		T222	30		T54	12
auto[0]	values[0]	values[6]	8	1			T88	8		-	-		-	-
auto[0]	values[0]	values[7]	56	1			T281	12		T193	10		T294	12
auto[0]	values[1]	values[0]	30	1			T234	10		T258	10		T295	10
auto[0]	values[1]	values[1]	48	1			T27	4		T210	26		T120	16
auto[0]	values[1]	values[2]	30	1			T126	4		T204	24		T296	2
auto[0]	values[1]	values[3]	48	1			T31	22		T192	2		T297	24
auto[0]	values[1]	values[4]	52	1			T79	6		T187	20		T93	12
auto[0]	values[1]	values[5]	50	1			T286	12		T178	16		T260	2
auto[0]	values[1]	values[6]	26	1			T298	16		T299	10		-	-
auto[0]	values[1]	values[7]	108	1			T252	14		T300	14		T196	32
auto[0]	values[2]	values[0]	44	1			T84	26		T301	8		T259	10
auto[0]	values[2]	values[1]	50	1			T218	4		T243	20		T302	26
auto[0]	values[2]	values[3]	6	1			T241	4		T197	2		-	-
auto[0]	values[2]	values[4]	36	1			T247	16		T211	12		T274	8
auto[0]	values[2]	values[5]	74	1			T7	10		T271	6		T250	6
auto[0]	values[2]	values[6]	12	1			T177	12		-	-		-	-
auto[0]	values[2]	values[7]	82	1			T184	8		T170	14		T119	16
auto[0]	values[3]	values[0]	64	1			T2	22		T219	26		T280	2
auto[0]	values[3]	values[1]	80	1			T45	26		T57	18		T121	16
auto[0]	values[3]	values[2]	32	1			T287	24		T303	2		T251	6
auto[0]	values[3]	values[3]	26	1			T185	2		T183	16		T209	6
auto[0]	values[3]	values[4]	4	1			T304	4		-	-		-	-
auto[0]	values[3]	values[5]	16	1			T8	2		T92	2		T91	2
auto[0]	values[3]	values[6]	72	1			T87	8		T285	24		T228	14
auto[0]	values[3]	values[7]	26	1			T224	26		-	-		-	-
auto[0]	values[4]	values[0]	10	1			T282	10		-	-		-	-
auto[0]	values[4]	values[2]	42	1			T207	8		T191	14		T242	20
auto[0]	values[4]	values[3]	32	1			T269	26		T278	6		-	-
auto[0]	values[4]	values[4]	36	1			T176	22		T244	14		-	-
auto[0]	values[4]	values[5]	30	1			T83	6		T214	8		T305	2
auto[0]	values[4]	values[6]	68	1			T195	4		T245	24		T277	24
auto[0]	values[4]	values[7]	74	1			T10	20		T29	2		T188	4
auto[0]	values[5]	values[0]	50	1			T173	20		T253	20		T85	10
auto[0]	values[5]	values[1]	24	1			T268	2		T306	18		T273	4
auto[0]	values[5]	values[2]	22	1			T307	16		T308	6		-	-
auto[0]	values[5]	values[3]	10	1			T309	10		-	-		-	-
auto[0]	values[5]	values[4]	60	1			T28	2		T58	32		T263	8
auto[0]	values[5]	values[5]	30	1			T63	28		T239	2		-	-
auto[0]	values[5]	values[6]	86	1			T96	36		T310	22		T249	8
auto[0]	values[5]	values[7]	72	1			T61	22		T311	4		T312	22
auto[0]	values[6]	values[0]	18	1			T313	18		-	-		-	-
auto[0]	values[6]	values[1]	48	1			T30	20		T229	22		T26	6
auto[0]	values[6]	values[2]	14	1			T314	2		T230	6		T201	6
auto[0]	values[6]	values[3]	14	1			T4	8		T189	2		T206	4
auto[0]	values[6]	values[4]	30	1			T78	4		T315	26		-	-
auto[0]	values[6]	values[5]	44	1			T238	26		T316	18		-	-
auto[0]	values[6]	values[7]	34	1			T94	28		T317	6		-	-
auto[0]	values[7]	values[0]	32	1			T125	6		T248	12		T270	2
auto[0]	values[7]	values[1]	84	1			T262	8		T217	6		T181	10
auto[0]	values[7]	values[2]	2	1			T318	2		-	-		-	-
auto[0]	values[7]	values[4]	58	1			T221	2		T319	16		T320	16
auto[0]	values[7]	values[5]	16	1			T321	16		-	-		-	-
auto[0]	values[7]	values[6]	42	1			T322	4		T323	30		T194	8
auto[0]	values[7]	values[7]	62	1			T11	8		T179	18		T220	12
auto[1]	values[0]	values[2]	18	1			T69	16		T324	2		-	-
auto[1]	values[0]	values[3]	28	1			T68	24		T290	4		-	-
auto[1]	values[0]	values[6]	2	1			T325	2		-	-		-	-
auto[1]	values[1]	values[1]	32	1			T272	12		T326	20		-	-
auto[1]	values[1]	values[3]	46	1			T215	30		T67	16		-	-
auto[1]	values[1]	values[4]	22	1			T72	22		-	-		-	-
auto[1]	values[1]	values[5]	6	1			T283	6		-	-		-	-
auto[1]	values[2]	values[1]	2	1			T267	2		-	-		-	-
auto[1]	values[2]	values[2]	54	1			T186	20		T232	34		-	-
auto[1]	values[2]	values[5]	26	1			T246	26		-	-		-	-
auto[1]	values[3]	values[6]	20	1			T265	20		-	-		-	-
auto[1]	values[3]	values[7]	46	1			T51	18		T327	28		-	-
auto[1]	values[4]	values[0]	10	1			T328	10		-	-		-	-
auto[1]	values[4]	values[1]	28	1			T190	28		-	-		-	-
auto[1]	values[4]	values[2]	6	1			T329	6		-	-		-	-
auto[1]	values[4]	values[3]	40	1			T254	36		T279	4		-	-
auto[1]	values[4]	values[4]	18	1			T70	18		-	-		-	-
auto[1]	values[4]	values[6]	62	1			T75	14		T330	30		T331	18
auto[1]	values[4]	values[7]	28	1			T216	28		-	-		-	-
auto[1]	values[5]	values[2]	4	1			T231	4		-	-		-	-
auto[1]	values[5]	values[3]	14	1			T212	14		-	-		-	-
auto[1]	values[5]	values[4]	38	1			T332	16		T333	22		-	-
auto[1]	values[5]	values[5]	12	1			T73	12		-	-		-	-
auto[1]	values[5]	values[6]	10	1			T65	10		-	-		-	-
auto[1]	values[5]	values[7]	26	1			T205	26		-	-		-	-
auto[1]	values[6]	values[1]	84	1			T334	36		T335	34		T26	14
auto[1]	values[6]	values[4]	44	1			T71	32		T336	12		-	-
auto[1]	values[6]	values[5]	38	1			T337	14		T292	24		-	-
auto[1]	values[6]	values[7]	30	1			T255	22		T226	8		-	-
auto[1]	values[7]	values[0]	28	1			T64	28		-	-		-	-
auto[1]	values[7]	values[2]	32	1			T66	32		-	-		-	-
auto[1]	values[7]	values[4]	24	1			T74	24		-	-		-	-
auto[1]	values[7]	values[5]	46	1			T62	22		T291	24		-	-
auto[1]	values[7]	values[6]	36	1			T338	10		T289	26		-	-