Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.04	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	8	52	86.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	8	52	86.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	130	1			T87	4		T185	2		T188	2
auto[ReadAddrCrossIntoMailbox]	30	1			T355	2		T319	2		T191	6
auto[ReadAddrCrossOutOfMailbox]	32	1			T355	2		T306	6		T316	4
auto[ReadAddrCrossAllMailbox]	22	1			T209	2		T355	8		T191	2
auto[ReadAddrOutsideMailbox]	861	1			T4	2		T7	4		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

537

1

T4

1

T7

2

T8

1

auto[1]

538

1

T4

1

T7

2

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	188	1			T12	4		T87	4		T45	2
read_ops[0x0b]	186	1			T4	2		T11	4		T12	2
read_ops[0x3b]	209	1			T7	4		T8	2		T12	8
read_ops[0x6b]	160	1			T12	4		T45	4		T63	2
read_ops[0xbb]	183	1			T12	6		T63	2		T184	4
read_ops[0xeb]	149	1			T61	2		T45	8		T30	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	8	52	86.67	8

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2
[read_ops[0x6b]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2
[read_ops[0xeb]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	13	1			T87	2		T185	1		T119	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T87	2		T185	1		T119	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T191	1		T356	1		T284	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T191	1		T356	1		T284	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T316	1		T284	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T316	1		T284	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T355	3		T191	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T355	3		T191	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T12	2		T45	1		T83	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	72	1			T12	2		T45	1		T83	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T219	2		T285	1		T248	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T219	2		T285	1		T248	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T299	3		T284	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T299	3		T284	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T306	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T306	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	80	1			T4	1		T11	2		T12	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	80	1			T4	1		T11	2		T12	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T119	1		T219	1		T229	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T119	1		T219	1		T229	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T355	1		T191	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T355	1		T191	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T355	1		T278	1		T357	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T355	1		T278	1		T357	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T355	1		T278	1		T299	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T355	1		T278	1		T299	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	82	1			T7	2		T8	1		T12	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	83	1			T7	2		T8	1		T12	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T188	1		T229	1		T316	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T188	1		T229	1		T316	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T316	1		T284	2		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T316	1		T284	2		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	73	1			T12	2		T45	2		T63	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	73	1			T12	2		T45	2		T63	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T207	1		T219	1		T285	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T207	1		T219	1		T285	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T319	1		T306	2		T320	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T319	1		T306	2		T320	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T306	1		T320	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T306	1		T320	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T209	1		T320	1		T278	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T209	1		T320	1		T278	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	64	1			T12	3		T63	1		T184	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	63	1			T12	3		T63	1		T184	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T229	2		T196	4		T248	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T229	2		T196	4		T248	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T320	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T320	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T306	1		T284	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T306	1		T284	1		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	59	1			T61	1		T45	4		T30	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	60	1			T61	1		T45	4		T30	1