Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	306126	1			T1	1528		T2	1		T3	5640
all_pins[1]	306126	1			T1	1528		T2	1		T3	5640
all_pins[2]	306126	1			T1	1528		T2	1		T3	5640
all_pins[3]	306126	1			T1	1528		T2	1		T3	5640
all_pins[4]	306126	1			T1	1528		T2	1		T3	5640
all_pins[5]	306126	1			T1	1528		T2	1		T3	5640
all_pins[6]	306126	1			T1	1528		T2	1		T3	5640
all_pins[7]	306126	1			T1	1528		T2	1		T3	5640

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2448111	1			T1	12224		T2	8		T3	45120
values[0x1]	897	1			T19	15		T35	29		T36	4
transitions[0x0=>0x1]	688	1			T19	10		T35	23		T36	3
transitions[0x1=>0x0]	700	1			T19	11		T35	23		T36	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	306001	1			T1	1528		T2	1		T3	5640
all_pins[0]	values[0x1]	125	1			T19	2		T35	5		T36	1
all_pins[0]	transitions[0x0=>0x1]	102	1			T19	2		T35	5		T36	1
all_pins[0]	transitions[0x1=>0x0]	86	1			T19	1		T35	3		T37	3
all_pins[1]	values[0x0]	306017	1			T1	1528		T2	1		T3	5640
all_pins[1]	values[0x1]	109	1			T19	1		T35	3		T37	4
all_pins[1]	transitions[0x0=>0x1]	84	1			T19	1		T35	3		T37	3
all_pins[1]	transitions[0x1=>0x0]	78	1			T19	3		T35	1		T359	3
all_pins[2]	values[0x0]	306023	1			T1	1528		T2	1		T3	5640
all_pins[2]	values[0x1]	103	1			T19	3		T35	1		T37	1
all_pins[2]	transitions[0x0=>0x1]	76	1			T37	1		T359	5		T164	3
all_pins[2]	transitions[0x1=>0x0]	103	1			T19	2		T35	2		T359	2
all_pins[3]	values[0x0]	305996	1			T1	1528		T2	1		T3	5640
all_pins[3]	values[0x1]	130	1			T19	5		T35	3		T359	3
all_pins[3]	transitions[0x0=>0x1]	103	1			T19	5		T35	3		T359	3
all_pins[3]	transitions[0x1=>0x0]	99	1			T35	2		T36	1		T37	5
all_pins[4]	values[0x0]	306000	1			T1	1528		T2	1		T3	5640
all_pins[4]	values[0x1]	126	1			T35	2		T36	1		T37	5
all_pins[4]	transitions[0x0=>0x1]	103	1			T35	1		T37	5		T359	2
all_pins[4]	transitions[0x1=>0x0]	90	1			T35	4		T36	1		T37	2
all_pins[5]	values[0x0]	306013	1			T1	1528		T2	1		T3	5640
all_pins[5]	values[0x1]	113	1			T35	5		T36	2		T37	2
all_pins[5]	transitions[0x0=>0x1]	85	1			T35	3		T36	2		T37	2
all_pins[5]	transitions[0x1=>0x0]	66	1			T19	1		T35	2		T37	1
all_pins[6]	values[0x0]	306032	1			T1	1528		T2	1		T3	5640
all_pins[6]	values[0x1]	94	1			T19	1		T35	4		T37	1
all_pins[6]	transitions[0x0=>0x1]	75	1			T19	1		T35	4		T37	1
all_pins[6]	transitions[0x1=>0x0]	78	1			T19	3		T35	6		T37	1
all_pins[7]	values[0x0]	306029	1			T1	1528		T2	1		T3	5640
all_pins[7]	values[0x1]	97	1			T19	3		T35	6		T37	1
all_pins[7]	transitions[0x0=>0x1]	60	1			T19	1		T35	4		T37	1
all_pins[7]	transitions[0x1=>0x0]	100	1			T19	1		T35	3		T36	1