Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	55	73	57.03

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	55	73	57.03	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	418	1			T4	8		T79	6		T184	8
values[1]	352	1			T92	2		T62	22		T125	6
values[2]	500	1			T7	10		T65	10		T66	32
values[3]	506	1			T87	8		T30	20		T64	28
values[4]	538	1			T8	2		T78	4		T83	6
values[5]	546	1			T10	20		T12	30		T45	26
values[6]	184	1			T61	22		T185	2		T119	16
values[7]	484	1			T2	22		T11	8		T27	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	752	1			T4	8		T10	20		T12	30
values[1]	368	1			T79	6		T184	8		T186	20
values[2]	458	1			T78	4		T187	20		T188	4
values[3]	404	1			T11	8		T62	22		T45	26
values[4]	418	1			T61	22		T94	28		T30	20
values[5]	374	1			T8	2		T87	8		T63	28
values[6]	442	1			T2	22		T27	4		T185	2
values[7]	312	1			T7	10		T95	4		T189	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3482

1

T2

22

T4

8

T7

10

auto[1]

46

1

T62

6

T64

4

T66

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	55	73	57.03	55

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[1]]	0	1	1
[auto[0]]	[values[6]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[2]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[3]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[4] , values[5]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	14
[auto[1]]	[values[6]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[6]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	158	1			T4	8		T190	28		T73	10
auto[0]	values[0]	values[1]	32	1			T79	6		T184	8		T191	14
auto[0]	values[0]	values[2]	64	1			T192	2		T57	18		T193	10
auto[0]	values[0]	values[3]	44	1			T96	36		T194	8		-	-
auto[0]	values[0]	values[4]	56	1			T195	4		T196	32		T197	2
auto[0]	values[0]	values[5]	4	1			T198	2		T91	2		-	-
auto[0]	values[0]	values[6]	28	1			T71	28		-	-		-	-
auto[0]	values[0]	values[7]	24	1			T199	22		T200	2		-	-
auto[0]	values[1]	values[0]	14	1			T92	2		T201	6		T202	6
auto[0]	values[1]	values[1]	10	1			T203	10		-	-		-	-
auto[0]	values[1]	values[2]	50	1			T204	24		T205	26		-	-
auto[0]	values[1]	values[3]	20	1			T62	16		T206	4		-	-
auto[0]	values[1]	values[4]	18	1			T125	6		T69	12		-	-
auto[0]	values[1]	values[5]	64	1			T207	8		T208	14		T209	6
auto[0]	values[1]	values[6]	68	1			T72	18		T210	26		T211	12
auto[0]	values[1]	values[7]	92	1			T68	24		T212	14		T213	24
auto[0]	values[2]	values[0]	154	1			T214	8		T84	26		T215	30
auto[0]	values[2]	values[2]	66	1			T216	28		T217	6		T218	4
auto[0]	values[2]	values[3]	50	1			T219	26		T220	12		T221	2
auto[0]	values[2]	values[4]	40	1			T65	10		T222	30		-	-
auto[0]	values[2]	values[5]	56	1			T66	28		T223	28		-	-
auto[0]	values[2]	values[6]	60	1			T224	26		T225	16		T226	8
auto[0]	values[2]	values[7]	70	1			T7	10		T189	2		T227	24
auto[0]	values[3]	values[0]	112	1			T64	24		T179	18		T228	14
auto[0]	values[3]	values[1]	84	1			T229	22		T230	6		T231	4
auto[0]	values[3]	values[2]	46	1			T93	12		T232	34		-	-
auto[0]	values[3]	values[3]	56	1			T88	8		T233	34		T234	10
auto[0]	values[3]	values[4]	104	1			T30	20		T173	20		T235	2
auto[0]	values[3]	values[5]	42	1			T87	8		T236	14		T237	10
auto[0]	values[3]	values[6]	44	1			T238	26		T51	18		-	-
auto[0]	values[3]	values[7]	12	1			T177	12		-	-		-	-
auto[0]	values[4]	values[0]	76	1			T239	2		T182	24		T240	30
auto[0]	values[4]	values[1]	38	1			T54	12		T241	4		T242	20
auto[0]	values[4]	values[2]	74	1			T78	4		T187	20		T243	20
auto[0]	values[4]	values[3]	72	1			T83	6		T31	22		T244	14
auto[0]	values[4]	values[4]	116	1			T94	28		T245	24		T246	26
auto[0]	values[4]	values[5]	78	1			T8	2		T63	28		T28	2
auto[0]	values[4]	values[6]	64	1			T247	16		T248	12		T249	8
auto[0]	values[4]	values[7]	16	1			T95	4		T250	6		T251	6
auto[0]	values[5]	values[0]	110	1			T10	20		T12	30		T75	10
auto[0]	values[5]	values[1]	126	1			T186	20		T252	14		T253	20
auto[0]	values[5]	values[2]	106	1			T254	36		T255	22		T256	6
auto[0]	values[5]	values[3]	72	1			T45	26		T178	16		T257	2
auto[0]	values[5]	values[4]	42	1			T176	22		T258	10		T259	10
auto[0]	values[5]	values[5]	54	1			T260	2		T183	16		T26	20
auto[0]	values[5]	values[6]	28	1			T261	12		T262	8		T263	8
auto[0]	values[5]	values[7]	4	1			T264	4		-	-		-	-
auto[0]	values[6]	values[2]	16	1			T70	16		-	-		-	-
auto[0]	values[6]	values[3]	48	1			T119	16		T265	20		T266	12
auto[0]	values[6]	values[4]	26	1			T61	22		T267	2		T268	2
auto[0]	values[6]	values[5]	50	1			T269	26		T270	2		T271	6
auto[0]	values[6]	values[6]	14	1			T185	2		T272	12		-	-
auto[0]	values[6]	values[7]	28	1			T67	16		T273	4		T274	8
auto[0]	values[7]	values[0]	112	1			T29	2		T53	32		T275	32
auto[0]	values[7]	values[1]	78	1			T276	4		T277	24		T278	6
auto[0]	values[7]	values[2]	34	1			T188	4		T279	4		T280	2
auto[0]	values[7]	values[3]	36	1			T11	8		T170	14		T281	12
auto[0]	values[7]	values[4]	10	1			T282	10		-	-		-	-
auto[0]	values[7]	values[5]	22	1			T283	6		T284	16		-	-
auto[0]	values[7]	values[6]	124	1			T2	22		T27	4		T285	24
auto[0]	values[7]	values[7]	66	1			T286	12		T287	24		T288	30
auto[1]	values[0]	values[0]	4	1			T73	2		T289	2		-	-
auto[1]	values[0]	values[6]	4	1			T71	4		-	-		-	-
auto[1]	values[1]	values[3]	6	1			T62	6		-	-		-	-
auto[1]	values[1]	values[4]	4	1			T69	4		-	-		-	-
auto[1]	values[1]	values[6]	6	1			T72	4		T290	2		-	-
auto[1]	values[2]	values[5]	4	1			T66	4		-	-		-	-
auto[1]	values[3]	values[0]	4	1			T64	4		-	-		-	-
auto[1]	values[3]	values[4]	2	1			T291	2		-	-		-	-
auto[1]	values[4]	values[0]	4	1			T292	4		-	-		-	-
auto[1]	values[5]	values[0]	4	1			T75	4		-	-		-	-
auto[1]	values[6]	values[2]	2	1			T70	2		-	-		-	-
auto[1]	values[7]	values[6]	2	1			T74	2		-	-		-	-