Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	1	3	75.00
Crosses	4	2	2	50.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_prev_wr_en	2	1	1	50.00	100	1	1	2
cp_wr_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	4	2	2	50.00	100	1	1	0

Summary for Variable cp_prev_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_prev_wr_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35

1

T27

4

T28

2

T31

6

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Summary for Variable cp_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wr_en

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34	1			T27	4		T28	2		T31	6
auto[1]	1	1			T26	1		-	-		-	-

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Summary for Cross cr_all

Samples crossed: cp_wr_en cp_prev_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_wr_en	cp_prev_wr_en	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

cp_wr_en

cp_prev_wr_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

34

1

T27

4

T28

2

T31

6

auto[1]

auto[0]

1

1

T26

1

-

-

-

-