Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1501

1

T1

1

T3

6

T15

7

auto[1]

1429

1

T3

5

T15

12

T16

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

725

1

T1

1

T3

9

T6

20

auto[1]

2205

1

T3

2

T15

19

T16

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2653

1

T1

1

T3

8

T15

19

auto[1]

277

1

T3

3

T6

12

T21

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	581	1			T3	3		T15	5		T16	2
valid[1]	616	1			T3	1		T15	2		T16	3
valid[2]	564	1			T1	1		T15	5		T16	3
valid[3]	584	1			T3	3		T15	4		T16	2
valid[4]	585	1			T3	4		T15	3		T16	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	54	1			T6	2		T106	3		T104	3
auto[0]	auto[0]	valid[0]	auto[1]	205	1			T15	1		T17	4		T103	3
auto[0]	auto[0]	valid[1]	auto[0]	43	1			T21	1		T106	1		T104	2
auto[0]	auto[0]	valid[1]	auto[1]	253	1			T3	1		T15	1		T16	2
auto[0]	auto[0]	valid[2]	auto[0]	50	1			T1	1		T21	1		T23	1
auto[0]	auto[0]	valid[2]	auto[1]	205	1			T15	1		T16	1		T17	11
auto[0]	auto[0]	valid[3]	auto[0]	49	1			T3	1		T106	4		T104	1
auto[0]	auto[0]	valid[3]	auto[1]	228	1			T15	4		T17	3		T103	4
auto[0]	auto[0]	valid[4]	auto[0]	53	1			T3	2		T106	3		T104	1
auto[0]	auto[0]	valid[4]	auto[1]	216	1			T17	4		T103	4		T109	2
auto[0]	auto[1]	valid[0]	auto[0]	33	1			T3	1		T104	1		T105	2
auto[0]	auto[1]	valid[0]	auto[1]	235	1			T3	1		T15	4		T16	2
auto[0]	auto[1]	valid[1]	auto[0]	39	1			T21	1		T23	3		T104	1
auto[0]	auto[1]	valid[1]	auto[1]	227	1			T15	1		T16	1		T17	5
auto[0]	auto[1]	valid[2]	auto[0]	47	1			T6	3		T23	2		T104	1
auto[0]	auto[1]	valid[2]	auto[1]	214	1			T15	4		T16	2		T17	3
auto[0]	auto[1]	valid[3]	auto[0]	38	1			T6	2		T106	5		T104	1
auto[0]	auto[1]	valid[3]	auto[1]	206	1			T16	2		T17	5		T103	4
auto[0]	auto[1]	valid[4]	auto[0]	42	1			T3	2		T6	1		T23	2
auto[0]	auto[1]	valid[4]	auto[1]	216	1			T15	3		T16	1		T17	7
auto[1]	auto[0]	valid[0]	auto[0]	28	1			T3	1		T104	1		T413	1
auto[1]	auto[0]	valid[1]	auto[0]	28	1			T6	2		T106	1		T104	1
auto[1]	auto[0]	valid[2]	auto[0]	24	1			T6	1		T104	2		T406	1
auto[1]	auto[0]	valid[3]	auto[0]	32	1			T3	1		T6	1		T104	1
auto[1]	auto[0]	valid[4]	auto[0]	33	1			T6	1		T21	1		T23	2
auto[1]	auto[1]	valid[0]	auto[0]	26	1			T6	1		T104	1		T101	1
auto[1]	auto[1]	valid[1]	auto[0]	26	1			T106	3		T104	1		T105	1
auto[1]	auto[1]	valid[2]	auto[0]	24	1			T6	1		T409	1		T411	1
auto[1]	auto[1]	valid[3]	auto[0]	31	1			T3	1		T21	1		T23	1
auto[1]	auto[1]	valid[4]	auto[0]	25	1			T6	5		T102	1		T391	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal