Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18069

1

T1

18

T3

211

T13

11

auto[1]

20958

1

T3

35

T15

19

T16

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32506

1

T1

12

T3

162

T13

8

auto[1]

6521

1

T1

6

T3

84

T13

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20250	1			T1	6		T3	125		T13	7
others[1]	3211	1			T1	4		T3	30		T17	49
others[2]	3224	1			T1	2		T3	21		T13	1
others[3]	3882	1			T1	2		T3	25		T13	1
interest[1]	2169	1			T3	7		T17	24		T6	26
interest[4]	13534	1			T1	6		T3	81		T13	5
interest[64]	6291	1			T1	4		T3	38		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5839	1			T1	5		T3	64		T13	5
auto[0]	auto[0]	others[1]	994	1			T1	3		T3	18		T6	30
auto[0]	auto[0]	others[2]	1014	1			T1	1		T3	10		T13	1
auto[0]	auto[0]	others[3]	1123	1			T1	1		T3	15		T6	31
auto[0]	auto[0]	interest[1]	633	1			T3	4		T6	16		T20	1
auto[0]	auto[0]	interest[4]	3830	1			T1	5		T3	42		T13	4
auto[0]	auto[0]	interest[64]	1945	1			T1	2		T3	16		T13	2
auto[0]	auto[1]	others[0]	11074	1			T3	19		T15	19		T16	11
auto[0]	auto[1]	others[1]	1705	1			T3	4		T17	49		T103	23
auto[0]	auto[1]	others[2]	1687	1			T3	3		T17	61		T103	20
auto[0]	auto[1]	others[3]	2085	1			T3	3		T17	68		T103	18
auto[0]	auto[1]	interest[1]	1132	1			T17	24		T103	17		T76	4
auto[0]	auto[1]	interest[4]	7478	1			T3	10		T15	19		T16	11
auto[0]	auto[1]	interest[64]	3275	1			T3	6		T17	95		T103	50
auto[1]	auto[0]	others[0]	3337	1			T1	1		T3	42		T13	2
auto[1]	auto[0]	others[1]	512	1			T1	1		T3	8		T6	4
auto[1]	auto[0]	others[2]	523	1			T1	1		T3	8		T6	15
auto[1]	auto[0]	others[3]	674	1			T1	1		T3	7		T13	1
auto[1]	auto[0]	interest[1]	404	1			T3	3		T6	10		T20	2
auto[1]	auto[0]	interest[4]	2226	1			T1	1		T3	29		T13	1
auto[1]	auto[0]	interest[64]	1071	1			T1	2		T3	16		T6	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal